24#define DEBUG_TYPE "riscv-dead-defs"
25#define RISCV_DEAD_REG_DEF_NAME "RISC-V Dead register definitions"
27STATISTIC(NumDeadDefsReplaced,
"Number of dead definitions replaced");
51char RISCVDeadRegisterDefinitions::ID = 0;
56 return new RISCVDeadRegisterDefinitions();
59bool RISCVDeadRegisterDefinitions::runOnMachineFunction(
MachineFunction &MF) {
66 LLVM_DEBUG(
dbgs() <<
"***** RISCVDeadRegisterDefinitions *****\n");
68 bool MadeChange =
false;
74 if (!
Desc.mayLoad() && !
Desc.mayStore() &&
75 !
Desc.hasUnmodeledSideEffects() &&
76 MI.getOpcode() != RISCV::PseudoVSETVLI &&
77 MI.getOpcode() != RISCV::PseudoVSETIVLI)
80 if (
MI.getOpcode() == RISCV::PseudoVSETVLIX0)
82 for (
int I = 0, E =
Desc.getNumDefs();
I != E; ++
I) {
87 if (
MI.isRegTiedToUseOperand(
I)) {
97 if (!(RC && RC->
contains(RISCV::X0))) {
102 LIS.removeInterval(Reg);
106 ++NumDeadDefsReplaced;
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
#define RISCV_DEAD_REG_DEF_NAME
INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME, false, false) char RISCVCoalesceVSETVLI const LiveIntervals * LIS
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createRISCVDeadRegisterDefinitionsPass()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Description of the encoding of one expression Op.