LLVM 19.0.0git
MachineInstr.h
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1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
20#include "llvm/ADT/ilist.h"
21#include "llvm/ADT/ilist_node.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/MC/MCInstrDesc.h"
30#include "llvm/MC/MCSymbol.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>
38
39namespace llvm {
40
41class DILabel;
42class Instruction;
43class MDNode;
44class AAResults;
45template <typename T> class ArrayRef;
46class DIExpression;
47class DILocalVariable;
48class MachineBasicBlock;
49class MachineFunction;
50class MachineRegisterInfo;
51class ModuleSlotTracker;
52class raw_ostream;
53template <typename T> class SmallVectorImpl;
54class SmallBitVector;
55class StringRef;
56class TargetInstrInfo;
57class TargetRegisterClass;
58class TargetRegisterInfo;
59
60//===----------------------------------------------------------------------===//
61/// Representation of each machine instruction.
62///
63/// This class isn't a POD type, but it must have a trivial destructor. When a
64/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
65/// without having their destructor called.
66///
68 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
69 ilist_sentinel_tracking<true>> {
70public:
72
73 /// Flags to specify different kinds of comments to output in
74 /// assembly code. These flags carry semantic information not
75 /// otherwise easily derivable from the IR text.
76 ///
78 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
80 TAsmComments = 0x4 // Target Asm comments should start from this value.
81 };
82
83 enum MIFlag {
85 FrameSetup = 1 << 0, // Instruction is used as a part of
86 // function frame setup code.
87 FrameDestroy = 1 << 1, // Instruction is used as a part of
88 // function frame destruction code.
89 BundledPred = 1 << 2, // Instruction has bundled predecessors.
90 BundledSucc = 1 << 3, // Instruction has bundled successors.
91 FmNoNans = 1 << 4, // Instruction does not support Fast
92 // math nan values.
93 FmNoInfs = 1 << 5, // Instruction does not support Fast
94 // math infinity values.
95 FmNsz = 1 << 6, // Instruction is not required to retain
96 // signed zero values.
97 FmArcp = 1 << 7, // Instruction supports Fast math
98 // reciprocal approximations.
99 FmContract = 1 << 8, // Instruction supports Fast math
100 // contraction operations like fma.
101 FmAfn = 1 << 9, // Instruction may map to Fast math
102 // intrinsic approximation.
103 FmReassoc = 1 << 10, // Instruction supports Fast math
104 // reassociation of operand order.
105 NoUWrap = 1 << 11, // Instruction supports binary operator
106 // no unsigned wrap.
107 NoSWrap = 1 << 12, // Instruction supports binary operator
108 // no signed wrap.
109 IsExact = 1 << 13, // Instruction supports division is
110 // known to be exact.
111 NoFPExcept = 1 << 14, // Instruction does not raise
112 // floatint-point exceptions.
113 NoMerge = 1 << 15, // Passes that drop source location info
114 // (e.g. branch folding) should skip
115 // this instruction.
116 Unpredictable = 1 << 16, // Instruction with unpredictable condition.
117 NoConvergent = 1 << 17, // Call does not require convergence guarantees.
118 NonNeg = 1 << 18, // The operand is non-negative.
119 Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
120 };
121
122private:
123 const MCInstrDesc *MCID; // Instruction descriptor.
124 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
125
126 // Operands are allocated by an ArrayRecycler.
127 MachineOperand *Operands = nullptr; // Pointer to the first operand.
128
129#define LLVM_MI_NUMOPERANDS_BITS 24
130#define LLVM_MI_FLAGS_BITS 24
131#define LLVM_MI_ASMPRINTERFLAGS_BITS 8
132
133 /// Number of operands on instruction.
135
136 // OperandCapacity has uint8_t size, so it should be next to NumOperands
137 // to properly pack.
138 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
139 OperandCapacity CapOperands; // Capacity of the Operands array.
140
141 /// Various bits of additional information about the machine instruction.
143
144 /// Various bits of information used by the AsmPrinter to emit helpful
145 /// comments. This is *not* semantic information. Do not use this for
146 /// anything other than to convey comment information to AsmPrinter.
147 uint8_t AsmPrinterFlags : LLVM_MI_ASMPRINTERFLAGS_BITS;
148
149 /// Internal implementation detail class that provides out-of-line storage for
150 /// extra info used by the machine instruction when this info cannot be stored
151 /// in-line within the instruction itself.
152 ///
153 /// This has to be defined eagerly due to the implementation constraints of
154 /// `PointerSumType` where it is used.
155 class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
156 MCSymbol *, MDNode *, uint32_t> {
157 public:
158 static ExtraInfo *create(BumpPtrAllocator &Allocator,
159 ArrayRef<MachineMemOperand *> MMOs,
160 MCSymbol *PreInstrSymbol = nullptr,
161 MCSymbol *PostInstrSymbol = nullptr,
162 MDNode *HeapAllocMarker = nullptr,
163 MDNode *PCSections = nullptr,
164 uint32_t CFIType = 0) {
165 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
166 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
167 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
168 bool HasCFIType = CFIType != 0;
169 bool HasPCSections = PCSections != nullptr;
170 auto *Result = new (Allocator.Allocate(
171 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
172 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
173 HasHeapAllocMarker + HasPCSections, HasCFIType),
174 alignof(ExtraInfo)))
175 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
176 HasHeapAllocMarker, HasPCSections, HasCFIType);
177
178 // Copy the actual data into the trailing objects.
179 std::copy(MMOs.begin(), MMOs.end(),
180 Result->getTrailingObjects<MachineMemOperand *>());
181
182 if (HasPreInstrSymbol)
183 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
184 if (HasPostInstrSymbol)
185 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
186 PostInstrSymbol;
187 if (HasHeapAllocMarker)
188 Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
189 if (HasPCSections)
190 Result->getTrailingObjects<MDNode *>()[HasHeapAllocMarker] =
191 PCSections;
192 if (HasCFIType)
193 Result->getTrailingObjects<uint32_t>()[0] = CFIType;
194
195 return Result;
196 }
197
198 ArrayRef<MachineMemOperand *> getMMOs() const {
199 return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
200 }
201
202 MCSymbol *getPreInstrSymbol() const {
203 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
204 }
205
206 MCSymbol *getPostInstrSymbol() const {
207 return HasPostInstrSymbol
208 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
209 : nullptr;
210 }
211
212 MDNode *getHeapAllocMarker() const {
213 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
214 }
215
216 MDNode *getPCSections() const {
217 return HasPCSections
218 ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
219 : nullptr;
220 }
221
222 uint32_t getCFIType() const {
223 return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
224 }
225
226 private:
227 friend TrailingObjects;
228
229 // Description of the extra info, used to interpret the actual optional
230 // data appended.
231 //
232 // Note that this is not terribly space optimized. This leaves a great deal
233 // of flexibility to fit more in here later.
234 const int NumMMOs;
235 const bool HasPreInstrSymbol;
236 const bool HasPostInstrSymbol;
237 const bool HasHeapAllocMarker;
238 const bool HasPCSections;
239 const bool HasCFIType;
240
241 // Implement the `TrailingObjects` internal API.
242 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
243 return NumMMOs;
244 }
245 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
246 return HasPreInstrSymbol + HasPostInstrSymbol;
247 }
248 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
249 return HasHeapAllocMarker + HasPCSections;
250 }
251 size_t numTrailingObjects(OverloadToken<uint32_t>) const {
252 return HasCFIType;
253 }
254
255 // Just a boring constructor to allow us to initialize the sizes. Always use
256 // the `create` routine above.
257 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
258 bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType)
259 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
260 HasPostInstrSymbol(HasPostInstrSymbol),
261 HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
262 HasCFIType(HasCFIType) {}
263 };
264
265 /// Enumeration of the kinds of inline extra info available. It is important
266 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
267 /// it accessible as an `ArrayRef`.
268 enum ExtraInfoInlineKinds {
269 EIIK_MMO = 0,
270 EIIK_PreInstrSymbol,
271 EIIK_PostInstrSymbol,
272 EIIK_OutOfLine
273 };
274
275 // We store extra information about the instruction here. The common case is
276 // expected to be nothing or a single pointer (typically a MMO or a symbol).
277 // We work to optimize this common case by storing it inline here rather than
278 // requiring a separate allocation, but we fall back to an allocation when
279 // multiple pointers are needed.
280 PointerSumType<ExtraInfoInlineKinds,
281 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
282 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
283 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
284 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
285 Info;
286
287 DebugLoc DbgLoc; // Source line information.
288
289 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
290 /// defined by this instruction.
291 unsigned DebugInstrNum;
292
293 // Intrusive list support
294 friend struct ilist_traits<MachineInstr>;
296 void setParent(MachineBasicBlock *P) { Parent = P; }
297
298 /// This constructor creates a copy of the given
299 /// MachineInstr in the given MachineFunction.
301
302 /// This constructor create a MachineInstr and add the implicit operands.
303 /// It reserves space for number of operands specified by
304 /// MCInstrDesc. An explicit DebugLoc is supplied.
306 bool NoImp = false);
307
308 // MachineInstrs are pool-allocated and owned by MachineFunction.
309 friend class MachineFunction;
310
311 void
312 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
313 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
314
315 static bool opIsRegDef(const MachineOperand &Op) {
316 return Op.isReg() && Op.isDef();
317 }
318
319 static bool opIsRegUse(const MachineOperand &Op) {
320 return Op.isReg() && Op.isUse();
321 }
322
323public:
324 MachineInstr(const MachineInstr &) = delete;
326 // Use MachineFunction::DeleteMachineInstr() instead.
327 ~MachineInstr() = delete;
328
329 const MachineBasicBlock* getParent() const { return Parent; }
330 MachineBasicBlock* getParent() { return Parent; }
331
332 /// Move the instruction before \p MovePos.
333 void moveBefore(MachineInstr *MovePos);
334
335 /// Return the function that contains the basic block that this instruction
336 /// belongs to.
337 ///
338 /// Note: this is undefined behaviour if the instruction does not have a
339 /// parent.
340 const MachineFunction *getMF() const;
342 return const_cast<MachineFunction *>(
343 static_cast<const MachineInstr *>(this)->getMF());
344 }
345
346 /// Return the asm printer flags bitvector.
347 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
348
349 /// Clear the AsmPrinter bitvector.
350 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
351
352 /// Return whether an AsmPrinter flag is set.
354 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
355 "Flag is out of range for the AsmPrinterFlags field");
356 return AsmPrinterFlags & Flag;
357 }
358
359 /// Set a flag for the AsmPrinter.
360 void setAsmPrinterFlag(uint8_t Flag) {
361 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
362 "Flag is out of range for the AsmPrinterFlags field");
363 AsmPrinterFlags |= Flag;
364 }
365
366 /// Clear specific AsmPrinter flags.
368 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
369 "Flag is out of range for the AsmPrinterFlags field");
370 AsmPrinterFlags &= ~Flag;
371 }
372
373 /// Return the MI flags bitvector.
375 return Flags;
376 }
377
378 /// Return whether an MI flag is set.
379 bool getFlag(MIFlag Flag) const {
380 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
381 "Flag is out of range for the Flags field");
382 return Flags & Flag;
383 }
384
385 /// Set a MI flag.
386 void setFlag(MIFlag Flag) {
387 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
388 "Flag is out of range for the Flags field");
389 Flags |= (uint32_t)Flag;
390 }
391
392 void setFlags(unsigned flags) {
393 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
394 "flags to be set are out of range for the Flags field");
395 // Filter out the automatically maintained flags.
396 unsigned Mask = BundledPred | BundledSucc;
397 Flags = (Flags & Mask) | (flags & ~Mask);
398 }
399
400 /// clearFlag - Clear a MI flag.
401 void clearFlag(MIFlag Flag) {
402 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
403 "Flag to clear is out of range for the Flags field");
404 Flags &= ~((uint32_t)Flag);
405 }
406
407 /// Return true if MI is in a bundle (but not the first MI in a bundle).
408 ///
409 /// A bundle looks like this before it's finalized:
410 /// ----------------
411 /// | MI |
412 /// ----------------
413 /// |
414 /// ----------------
415 /// | MI * |
416 /// ----------------
417 /// |
418 /// ----------------
419 /// | MI * |
420 /// ----------------
421 /// In this case, the first MI starts a bundle but is not inside a bundle, the
422 /// next 2 MIs are considered "inside" the bundle.
423 ///
424 /// After a bundle is finalized, it looks like this:
425 /// ----------------
426 /// | Bundle |
427 /// ----------------
428 /// |
429 /// ----------------
430 /// | MI * |
431 /// ----------------
432 /// |
433 /// ----------------
434 /// | MI * |
435 /// ----------------
436 /// |
437 /// ----------------
438 /// | MI * |
439 /// ----------------
440 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
441 /// a bundle, but the next three MIs are.
442 bool isInsideBundle() const {
443 return getFlag(BundledPred);
444 }
445
446 /// Return true if this instruction part of a bundle. This is true
447 /// if either itself or its following instruction is marked "InsideBundle".
448 bool isBundled() const {
450 }
451
452 /// Return true if this instruction is part of a bundle, and it is not the
453 /// first instruction in the bundle.
454 bool isBundledWithPred() const { return getFlag(BundledPred); }
455
456 /// Return true if this instruction is part of a bundle, and it is not the
457 /// last instruction in the bundle.
458 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
459
460 /// Bundle this instruction with its predecessor. This can be an unbundled
461 /// instruction, or it can be the first instruction in a bundle.
462 void bundleWithPred();
463
464 /// Bundle this instruction with its successor. This can be an unbundled
465 /// instruction, or it can be the last instruction in a bundle.
466 void bundleWithSucc();
467
468 /// Break bundle above this instruction.
469 void unbundleFromPred();
470
471 /// Break bundle below this instruction.
472 void unbundleFromSucc();
473
474 /// Returns the debug location id of this MachineInstr.
475 const DebugLoc &getDebugLoc() const { return DbgLoc; }
476
477 /// Return the operand containing the offset to be used if this DBG_VALUE
478 /// instruction is indirect; will be an invalid register if this value is
479 /// not indirect, and an immediate with value 0 otherwise.
481 assert(isNonListDebugValue() && "not a DBG_VALUE");
482 return getOperand(1);
483 }
485 assert(isNonListDebugValue() && "not a DBG_VALUE");
486 return getOperand(1);
487 }
488
489 /// Return the operand for the debug variable referenced by
490 /// this DBG_VALUE instruction.
491 const MachineOperand &getDebugVariableOp() const;
493
494 /// Return the debug variable referenced by
495 /// this DBG_VALUE instruction.
496 const DILocalVariable *getDebugVariable() const;
497
498 /// Return the operand for the complex address expression referenced by
499 /// this DBG_VALUE instruction.
502
503 /// Return the complex address expression referenced by
504 /// this DBG_VALUE instruction.
505 const DIExpression *getDebugExpression() const;
506
507 /// Return the debug label referenced by
508 /// this DBG_LABEL instruction.
509 const DILabel *getDebugLabel() const;
510
511 /// Fetch the instruction number of this MachineInstr. If it does not have
512 /// one already, a new and unique number will be assigned.
513 unsigned getDebugInstrNum();
514
515 /// Fetch instruction number of this MachineInstr -- but before it's inserted
516 /// into \p MF. Needed for transformations that create an instruction but
517 /// don't immediately insert them.
518 unsigned getDebugInstrNum(MachineFunction &MF);
519
520 /// Examine the instruction number of this MachineInstr. May be zero if
521 /// it hasn't been assigned a number yet.
522 unsigned peekDebugInstrNum() const { return DebugInstrNum; }
523
524 /// Set instruction number of this MachineInstr. Avoid using unless you're
525 /// deserializing this information.
526 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
527
528 /// Drop any variable location debugging information associated with this
529 /// instruction. Use when an instruction is modified in such a way that it no
530 /// longer defines the value it used to. Variable locations using that value
531 /// will be dropped.
532 void dropDebugNumber() { DebugInstrNum = 0; }
533
534 /// Emit an error referring to the source location of this instruction.
535 /// This should only be used for inline assembly that is somehow
536 /// impossible to compile. Other errors should have been handled much
537 /// earlier.
538 ///
539 /// If this method returns, the caller should try to recover from the error.
540 void emitError(StringRef Msg) const;
541
542 /// Returns the target instruction descriptor of this MachineInstr.
543 const MCInstrDesc &getDesc() const { return *MCID; }
544
545 /// Returns the opcode of this MachineInstr.
546 unsigned getOpcode() const { return MCID->Opcode; }
547
548 /// Retuns the total number of operands.
549 unsigned getNumOperands() const { return NumOperands; }
550
551 /// Returns the total number of operands which are debug locations.
552 unsigned getNumDebugOperands() const {
553 return std::distance(debug_operands().begin(), debug_operands().end());
554 }
555
556 const MachineOperand& getOperand(unsigned i) const {
557 assert(i < getNumOperands() && "getOperand() out of range!");
558 return Operands[i];
559 }
561 assert(i < getNumOperands() && "getOperand() out of range!");
562 return Operands[i];
563 }
564
566 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
567 return *(debug_operands().begin() + Index);
568 }
569 const MachineOperand &getDebugOperand(unsigned Index) const {
570 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
571 return *(debug_operands().begin() + Index);
572 }
573
574 /// Returns whether this debug value has at least one debug operand with the
575 /// register \p Reg.
577 return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
578 return Op.isReg() && Op.getReg() == Reg;
579 });
580 }
581
582 /// Returns a range of all of the operands that correspond to a debug use of
583 /// \p Reg.
584 template <typename Operand, typename Instruction>
585 static iterator_range<
586 filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
588 std::function<bool(Operand & Op)> OpUsesReg(
589 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
590 return make_filter_range(MI->debug_operands(), OpUsesReg);
591 }
593 std::function<bool(const MachineOperand &Op)>>>
596 const MachineInstr>(this, Reg);
597 }
599 std::function<bool(MachineOperand &Op)>>>
601 return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
602 this, Reg);
603 }
604
605 bool isDebugOperand(const MachineOperand *Op) const {
606 return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
607 }
608
609 unsigned getDebugOperandIndex(const MachineOperand *Op) const {
610 assert(isDebugOperand(Op) && "Expected a debug operand.");
611 return std::distance(adl_begin(debug_operands()), Op);
612 }
613
614 /// Returns the total number of definitions.
615 unsigned getNumDefs() const {
616 return getNumExplicitDefs() + MCID->implicit_defs().size();
617 }
618
619 /// Returns true if the instruction has implicit definition.
620 bool hasImplicitDef() const {
621 for (const MachineOperand &MO : implicit_operands())
622 if (MO.isDef() && MO.isImplicit())
623 return true;
624 return false;
625 }
626
627 /// Returns the implicit operands number.
628 unsigned getNumImplicitOperands() const {
630 }
631
632 /// Return true if operand \p OpIdx is a subregister index.
633 bool isOperandSubregIdx(unsigned OpIdx) const {
634 assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
635 if (isExtractSubreg() && OpIdx == 2)
636 return true;
637 if (isInsertSubreg() && OpIdx == 3)
638 return true;
639 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
640 return true;
641 if (isSubregToReg() && OpIdx == 3)
642 return true;
643 return false;
644 }
645
646 /// Returns the number of non-implicit operands.
647 unsigned getNumExplicitOperands() const;
648
649 /// Returns the number of non-implicit definitions.
650 unsigned getNumExplicitDefs() const;
651
652 /// iterator/begin/end - Iterate over all operands of a machine instruction.
655
657 mop_iterator operands_end() { return Operands + NumOperands; }
658
660 const_mop_iterator operands_end() const { return Operands + NumOperands; }
661
664 }
667 }
669 return make_range(operands_begin(),
671 }
673 return make_range(operands_begin(),
675 }
677 return make_range(explicit_operands().end(), operands_end());
678 }
680 return make_range(explicit_operands().end(), operands_end());
681 }
682 /// Returns a range over all operands that are used to determine the variable
683 /// location for this DBG_VALUE instruction.
685 assert((isDebugValueLike()) && "Must be a debug value instruction.");
686 return isNonListDebugValue()
689 }
690 /// \copydoc debug_operands()
692 assert((isDebugValueLike()) && "Must be a debug value instruction.");
693 return isNonListDebugValue()
696 }
697 /// Returns a range over all explicit operands that are register definitions.
698 /// Implicit definition are not included!
700 return make_range(operands_begin(),
702 }
703 /// \copydoc defs()
705 return make_range(operands_begin(),
707 }
708 /// Returns a range that includes all operands that are register uses.
709 /// This may include unrelated operands which are not register uses.
712 }
713 /// \copydoc uses()
716 }
720 }
724 }
725
730
731 /// Returns an iterator range over all operands that are (explicit or
732 /// implicit) register defs.
734 return make_filter_range(operands(), opIsRegDef);
735 }
736 /// \copydoc all_defs()
738 return make_filter_range(operands(), opIsRegDef);
739 }
740
741 /// Returns an iterator range over all operands that are (explicit or
742 /// implicit) register uses.
744 return make_filter_range(uses(), opIsRegUse);
745 }
746 /// \copydoc all_uses()
748 return make_filter_range(uses(), opIsRegUse);
749 }
750
751 /// Returns the number of the operand iterator \p I points to.
753 return I - operands_begin();
754 }
755
756 /// Access to memory operands of the instruction. If there are none, that does
757 /// not imply anything about whether the function accesses memory. Instead,
758 /// the caller must behave conservatively.
760 if (!Info)
761 return {};
762
763 if (Info.is<EIIK_MMO>())
764 return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
765
766 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
767 return EI->getMMOs();
768
769 return {};
770 }
771
772 /// Access to memory operands of the instruction.
773 ///
774 /// If `memoperands_begin() == memoperands_end()`, that does not imply
775 /// anything about whether the function accesses memory. Instead, the caller
776 /// must behave conservatively.
777 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
778
779 /// Access to memory operands of the instruction.
780 ///
781 /// If `memoperands_begin() == memoperands_end()`, that does not imply
782 /// anything about whether the function accesses memory. Instead, the caller
783 /// must behave conservatively.
784 mmo_iterator memoperands_end() const { return memoperands().end(); }
785
786 /// Return true if we don't have any memory operands which described the
787 /// memory access done by this instruction. If this is true, calling code
788 /// must be conservative.
789 bool memoperands_empty() const { return memoperands().empty(); }
790
791 /// Return true if this instruction has exactly one MachineMemOperand.
792 bool hasOneMemOperand() const { return memoperands().size() == 1; }
793
794 /// Return the number of memory operands.
795 unsigned getNumMemOperands() const { return memoperands().size(); }
796
797 /// Helper to extract a pre-instruction symbol if one has been added.
799 if (!Info)
800 return nullptr;
801 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
802 return S;
803 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
804 return EI->getPreInstrSymbol();
805
806 return nullptr;
807 }
808
809 /// Helper to extract a post-instruction symbol if one has been added.
811 if (!Info)
812 return nullptr;
813 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
814 return S;
815 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
816 return EI->getPostInstrSymbol();
817
818 return nullptr;
819 }
820
821 /// Helper to extract a heap alloc marker if one has been added.
823 if (!Info)
824 return nullptr;
825 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
826 return EI->getHeapAllocMarker();
827
828 return nullptr;
829 }
830
831 /// Helper to extract PCSections metadata target sections.
833 if (!Info)
834 return nullptr;
835 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
836 return EI->getPCSections();
837
838 return nullptr;
839 }
840
841 /// Helper to extract a CFI type hash if one has been added.
843 if (!Info)
844 return 0;
845 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
846 return EI->getCFIType();
847
848 return 0;
849 }
850
851 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
852 /// queries but they are bundle aware.
853
855 IgnoreBundle, // Ignore bundles
856 AnyInBundle, // Return true if any instruction in bundle has property
857 AllInBundle // Return true if all instructions in bundle have property
858 };
859
860 /// Return true if the instruction (or in the case of a bundle,
861 /// the instructions inside the bundle) has the specified property.
862 /// The first argument is the property being queried.
863 /// The second argument indicates whether the query should look inside
864 /// instruction bundles.
865 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
866 assert(MCFlag < 64 &&
867 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
868 // Inline the fast path for unbundled or bundle-internal instructions.
870 return getDesc().getFlags() & (1ULL << MCFlag);
871
872 // If this is the first instruction in a bundle, take the slow path.
873 return hasPropertyInBundle(1ULL << MCFlag, Type);
874 }
875
876 /// Return true if this is an instruction that should go through the usual
877 /// legalization steps.
880 }
881
882 /// Return true if this instruction can have a variable number of operands.
883 /// In this case, the variable operands will be after the normal
884 /// operands but before the implicit definitions and uses (if any are
885 /// present).
888 }
889
890 /// Set if this instruction has an optional definition, e.g.
891 /// ARM instructions which can set condition code if 's' bit is set.
894 }
895
896 /// Return true if this is a pseudo instruction that doesn't
897 /// correspond to a real machine instruction.
900 }
901
902 /// Return true if this instruction doesn't produce any output in the form of
903 /// executable instructions.
905 return hasProperty(MCID::Meta, Type);
906 }
907
910 }
911
912 /// Return true if this is an instruction that marks the end of an EH scope,
913 /// i.e., a catchpad or a cleanuppad instruction.
916 }
917
919 return hasProperty(MCID::Call, Type);
920 }
921
922 /// Return true if this is a call instruction that may have an associated
923 /// call site entry in the debug info.
925 /// Return true if copying, moving, or erasing this instruction requires
926 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
927 /// \ref eraseCallSiteInfo).
928 bool shouldUpdateCallSiteInfo() const;
929
930 /// Returns true if the specified instruction stops control flow
931 /// from executing the instruction immediately following it. Examples include
932 /// unconditional branches and return instructions.
935 }
936
937 /// Returns true if this instruction part of the terminator for a basic block.
938 /// Typically this is things like return and branch instructions.
939 ///
940 /// Various passes use this to insert code into the bottom of a basic block,
941 /// but before control flow occurs.
944 }
945
946 /// Returns true if this is a conditional, unconditional, or indirect branch.
947 /// Predicates below can be used to discriminate between
948 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
949 /// get more information.
952 }
953
954 /// Return true if this is an indirect branch, such as a
955 /// branch through a register.
958 }
959
960 /// Return true if this is a branch which may fall
961 /// through to the next instruction or may transfer control flow to some other
962 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
963 /// information about this branch.
966 }
967
968 /// Return true if this is a branch which always
969 /// transfers control flow to some other block. The
970 /// TargetInstrInfo::analyzeBranch method can be used to get more information
971 /// about this branch.
974 }
975
976 /// Return true if this instruction has a predicate operand that
977 /// controls execution. It may be set to 'always', or may be set to other
978 /// values. There are various methods in TargetInstrInfo that can be used to
979 /// control and modify the predicate in this instruction.
981 // If it's a bundle than all bundled instructions must be predicable for this
982 // to return true.
984 }
985
986 /// Return true if this instruction is a comparison.
989 }
990
991 /// Return true if this instruction is a move immediate
992 /// (including conditional moves) instruction.
995 }
996
997 /// Return true if this instruction is a register move.
998 /// (including moving values from subreg to reg)
1001 }
1002
1003 /// Return true if this instruction is a bitcast instruction.
1006 }
1007
1008 /// Return true if this instruction is a select instruction.
1010 return hasProperty(MCID::Select, Type);
1011 }
1012
1013 /// Return true if this instruction cannot be safely duplicated.
1014 /// For example, if the instruction has a unique labels attached
1015 /// to it, duplicating it would cause multiple definition errors.
1018 return true;
1020 }
1021
1022 /// Return true if this instruction is convergent.
1023 /// Convergent instructions can not be made control-dependent on any
1024 /// additional values.
1026 if (isInlineAsm()) {
1027 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1028 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1029 return true;
1030 }
1031 if (getFlag(NoConvergent))
1032 return false;
1034 }
1035
1036 /// Returns true if the specified instruction has a delay slot
1037 /// which must be filled by the code generator.
1040 }
1041
1042 /// Return true for instructions that can be folded as
1043 /// memory operands in other instructions. The most common use for this
1044 /// is instructions that are simple loads from memory that don't modify
1045 /// the loaded value in any way, but it can also be used for instructions
1046 /// that can be expressed as constant-pool loads, such as V_SETALLONES
1047 /// on x86, to allow them to be folded when it is beneficial.
1048 /// This should only be set on instructions that return a value in their
1049 /// only virtual register definition.
1052 }
1053
1054 /// Return true if this instruction behaves
1055 /// the same way as the generic REG_SEQUENCE instructions.
1056 /// E.g., on ARM,
1057 /// dX VMOVDRR rY, rZ
1058 /// is equivalent to
1059 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
1060 ///
1061 /// Note that for the optimizers to be able to take advantage of
1062 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
1063 /// override accordingly.
1066 }
1067
1068 /// Return true if this instruction behaves
1069 /// the same way as the generic EXTRACT_SUBREG instructions.
1070 /// E.g., on ARM,
1071 /// rX, rY VMOVRRD dZ
1072 /// is equivalent to two EXTRACT_SUBREG:
1073 /// rX = EXTRACT_SUBREG dZ, ssub_0
1074 /// rY = EXTRACT_SUBREG dZ, ssub_1
1075 ///
1076 /// Note that for the optimizers to be able to take advantage of
1077 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
1078 /// override accordingly.
1081 }
1082
1083 /// Return true if this instruction behaves
1084 /// the same way as the generic INSERT_SUBREG instructions.
1085 /// E.g., on ARM,
1086 /// dX = VSETLNi32 dY, rZ, Imm
1087 /// is equivalent to a INSERT_SUBREG:
1088 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
1089 ///
1090 /// Note that for the optimizers to be able to take advantage of
1091 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1092 /// override accordingly.
1095 }
1096
1097 //===--------------------------------------------------------------------===//
1098 // Side Effect Analysis
1099 //===--------------------------------------------------------------------===//
1100
1101 /// Return true if this instruction could possibly read memory.
1102 /// Instructions with this flag set are not necessarily simple load
1103 /// instructions, they may load a value and modify it, for example.
1105 if (isInlineAsm()) {
1106 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1107 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1108 return true;
1109 }
1111 }
1112
1113 /// Return true if this instruction could possibly modify memory.
1114 /// Instructions with this flag set are not necessarily simple store
1115 /// instructions, they may store a modified value based on their operands, or
1116 /// may not actually modify anything, for example.
1118 if (isInlineAsm()) {
1119 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1120 if (ExtraInfo & InlineAsm::Extra_MayStore)
1121 return true;
1122 }
1124 }
1125
1126 /// Return true if this instruction could possibly read or modify memory.
1128 return mayLoad(Type) || mayStore(Type);
1129 }
1130
1131 /// Return true if this instruction could possibly raise a floating-point
1132 /// exception. This is the case if the instruction is a floating-point
1133 /// instruction that can in principle raise an exception, as indicated
1134 /// by the MCID::MayRaiseFPException property, *and* at the same time,
1135 /// the instruction is used in a context where we expect floating-point
1136 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1137 bool mayRaiseFPException() const {
1140 }
1141
1142 //===--------------------------------------------------------------------===//
1143 // Flags that indicate whether an instruction can be modified by a method.
1144 //===--------------------------------------------------------------------===//
1145
1146 /// Return true if this may be a 2- or 3-address
1147 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1148 /// result if Y and Z are exchanged. If this flag is set, then the
1149 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1150 /// instruction.
1151 ///
1152 /// Note that this flag may be set on instructions that are only commutable
1153 /// sometimes. In these cases, the call to commuteInstruction will fail.
1154 /// Also note that some instructions require non-trivial modification to
1155 /// commute them.
1158 }
1159
1160 /// Return true if this is a 2-address instruction
1161 /// which can be changed into a 3-address instruction if needed. Doing this
1162 /// transformation can be profitable in the register allocator, because it
1163 /// means that the instruction can use a 2-address form if possible, but
1164 /// degrade into a less efficient form if the source and dest register cannot
1165 /// be assigned to the same register. For example, this allows the x86
1166 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1167 /// is the same speed as the shift but has bigger code size.
1168 ///
1169 /// If this returns true, then the target must implement the
1170 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1171 /// is allowed to fail if the transformation isn't valid for this specific
1172 /// instruction (e.g. shl reg, 4 on x86).
1173 ///
1176 }
1177
1178 /// Return true if this instruction requires
1179 /// custom insertion support when the DAG scheduler is inserting it into a
1180 /// machine basic block. If this is true for the instruction, it basically
1181 /// means that it is a pseudo instruction used at SelectionDAG time that is
1182 /// expanded out into magic code by the target when MachineInstrs are formed.
1183 ///
1184 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1185 /// is used to insert this into the MachineBasicBlock.
1188 }
1189
1190 /// Return true if this instruction requires *adjustment*
1191 /// after instruction selection by calling a target hook. For example, this
1192 /// can be used to fill in ARM 's' optional operand depending on whether
1193 /// the conditional flag register is used.
1196 }
1197
1198 /// Returns true if this instruction is a candidate for remat.
1199 /// This flag is deprecated, please don't use it anymore. If this
1200 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1201 /// verify the instruction is really rematerializable.
1203 // It's only possible to re-mat a bundle if all bundled instructions are
1204 // re-materializable.
1206 }
1207
1208 /// Returns true if this instruction has the same cost (or less) than a move
1209 /// instruction. This is useful during certain types of optimizations
1210 /// (e.g., remat during two-address conversion or machine licm)
1211 /// where we would like to remat or hoist the instruction, but not if it costs
1212 /// more than moving the instruction into the appropriate register. Note, we
1213 /// are not marking copies from and to the same register class with this flag.
1215 // Only returns true for a bundle if all bundled instructions are cheap.
1217 }
1218
1219 /// Returns true if this instruction source operands
1220 /// have special register allocation requirements that are not captured by the
1221 /// operand register classes. e.g. ARM::STRD's two source registers must be an
1222 /// even / odd pair, ARM::STM registers have to be in ascending order.
1223 /// Post-register allocation passes should not attempt to change allocations
1224 /// for sources of instructions with this flag.
1227 }
1228
1229 /// Returns true if this instruction def operands
1230 /// have special register allocation requirements that are not captured by the
1231 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1232 /// even / odd pair, ARM::LDM registers have to be in ascending order.
1233 /// Post-register allocation passes should not attempt to change allocations
1234 /// for definitions of instructions with this flag.
1237 }
1238
1240 CheckDefs, // Check all operands for equality
1241 CheckKillDead, // Check all operands including kill / dead markers
1242 IgnoreDefs, // Ignore all definitions
1243 IgnoreVRegDefs // Ignore virtual register definitions
1245
1246 /// Return true if this instruction is identical to \p Other.
1247 /// Two instructions are identical if they have the same opcode and all their
1248 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1249 /// Note that this means liveness related flags (dead, undef, kill) do not
1250 /// affect the notion of identical.
1251 bool isIdenticalTo(const MachineInstr &Other,
1252 MICheckType Check = CheckDefs) const;
1253
1254 /// Returns true if this instruction is a debug instruction that represents an
1255 /// identical debug value to \p Other.
1256 /// This function considers these debug instructions equivalent if they have
1257 /// identical variables, debug locations, and debug operands, and if the
1258 /// DIExpressions combined with the directness flags are equivalent.
1259 bool isEquivalentDbgInstr(const MachineInstr &Other) const;
1260
1261 /// Unlink 'this' from the containing basic block, and return it without
1262 /// deleting it.
1263 ///
1264 /// This function can not be used on bundled instructions, use
1265 /// removeFromBundle() to remove individual instructions from a bundle.
1267
1268 /// Unlink this instruction from its basic block and return it without
1269 /// deleting it.
1270 ///
1271 /// If the instruction is part of a bundle, the other instructions in the
1272 /// bundle remain bundled.
1274
1275 /// Unlink 'this' from the containing basic block and delete it.
1276 ///
1277 /// If this instruction is the header of a bundle, the whole bundle is erased.
1278 /// This function can not be used for instructions inside a bundle, use
1279 /// eraseFromBundle() to erase individual bundled instructions.
1280 void eraseFromParent();
1281
1282 /// Unlink 'this' from its basic block and delete it.
1283 ///
1284 /// If the instruction is part of a bundle, the other instructions in the
1285 /// bundle remain bundled.
1286 void eraseFromBundle();
1287
1288 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1289 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1290 bool isAnnotationLabel() const {
1291 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1292 }
1293
1294 /// Returns true if the MachineInstr represents a label.
1295 bool isLabel() const {
1296 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1297 }
1298
1299 bool isCFIInstruction() const {
1300 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1301 }
1302
1303 bool isPseudoProbe() const {
1304 return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1305 }
1306
1307 // True if the instruction represents a position in the function.
1308 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1309
1310 bool isNonListDebugValue() const {
1311 return getOpcode() == TargetOpcode::DBG_VALUE;
1312 }
1313 bool isDebugValueList() const {
1314 return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1315 }
1316 bool isDebugValue() const {
1318 }
1319 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1320 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1321 bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
1322 bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1323 bool isDebugInstr() const {
1324 return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1325 }
1327 return isDebugInstr() || isPseudoProbe();
1328 }
1329
1330 bool isDebugOffsetImm() const {
1332 }
1333
1334 /// A DBG_VALUE is indirect iff the location operand is a register and
1335 /// the offset operand is an immediate.
1337 return isDebugOffsetImm() && getDebugOperand(0).isReg();
1338 }
1339
1340 /// A DBG_VALUE is an entry value iff its debug expression contains the
1341 /// DW_OP_LLVM_entry_value operation.
1342 bool isDebugEntryValue() const;
1343
1344 /// Return true if the instruction is a debug value which describes a part of
1345 /// a variable as unavailable.
1346 bool isUndefDebugValue() const {
1347 if (!isDebugValue())
1348 return false;
1349 // If any $noreg locations are given, this DV is undef.
1350 for (const MachineOperand &Op : debug_operands())
1351 if (Op.isReg() && !Op.getReg().isValid())
1352 return true;
1353 return false;
1354 }
1355
1357 return getOpcode() == TargetOpcode::JUMP_TABLE_DEBUG_INFO;
1358 }
1359
1360 bool isPHI() const {
1361 return getOpcode() == TargetOpcode::PHI ||
1362 getOpcode() == TargetOpcode::G_PHI;
1363 }
1364 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1365 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1366 bool isInlineAsm() const {
1367 return getOpcode() == TargetOpcode::INLINEASM ||
1368 getOpcode() == TargetOpcode::INLINEASM_BR;
1369 }
1370 /// Returns true if the register operand can be folded with a load or store
1371 /// into a frame index. Does so by checking the InlineAsm::Flag immediate
1372 /// operand at OpId - 1.
1373 bool mayFoldInlineAsmRegOp(unsigned OpId) const;
1374
1375 bool isStackAligningInlineAsm() const;
1377
1378 bool isInsertSubreg() const {
1379 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1380 }
1381
1382 bool isSubregToReg() const {
1383 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1384 }
1385
1386 bool isRegSequence() const {
1387 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1388 }
1389
1390 bool isBundle() const {
1391 return getOpcode() == TargetOpcode::BUNDLE;
1392 }
1393
1394 bool isCopy() const {
1395 return getOpcode() == TargetOpcode::COPY;
1396 }
1397
1398 bool isFullCopy() const {
1399 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1400 }
1401
1402 bool isExtractSubreg() const {
1403 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1404 }
1405
1406 /// Return true if the instruction behaves like a copy.
1407 /// This does not include native copy instructions.
1408 bool isCopyLike() const {
1409 return isCopy() || isSubregToReg();
1410 }
1411
1412 /// Return true is the instruction is an identity copy.
1413 bool isIdentityCopy() const {
1414 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1416 }
1417
1418 /// Return true if this is a transient instruction that is either very likely
1419 /// to be eliminated during register allocation (such as copy-like
1420 /// instructions), or if this instruction doesn't have an execution-time cost.
1421 bool isTransient() const {
1422 switch (getOpcode()) {
1423 default:
1424 return isMetaInstruction();
1425 // Copy-like instructions are usually eliminated during register allocation.
1426 case TargetOpcode::PHI:
1427 case TargetOpcode::G_PHI:
1428 case TargetOpcode::COPY:
1429 case TargetOpcode::INSERT_SUBREG:
1430 case TargetOpcode::SUBREG_TO_REG:
1431 case TargetOpcode::REG_SEQUENCE:
1432 return true;
1433 }
1434 }
1435
1436 /// Return the number of instructions inside the MI bundle, excluding the
1437 /// bundle header.
1438 ///
1439 /// This is the number of instructions that MachineBasicBlock::iterator
1440 /// skips, 0 for unbundled instructions.
1441 unsigned getBundleSize() const;
1442
1443 /// Return true if the MachineInstr reads the specified register.
1444 /// If TargetRegisterInfo is non-null, then it also checks if there
1445 /// is a read of a super-register.
1446 /// This does not count partial redefines of virtual registers as reads:
1447 /// %reg1024:6 = OP.
1449 const TargetRegisterInfo *TRI = nullptr) const {
1450 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1451 }
1452
1453 /// Return true if the MachineInstr reads the specified virtual register.
1454 /// Take into account that a partial define is a
1455 /// read-modify-write operation.
1457 return readsWritesVirtualRegister(Reg).first;
1458 }
1459
1460 /// Return a pair of bools (reads, writes) indicating if this instruction
1461 /// reads or writes Reg. This also considers partial defines.
1462 /// If Ops is not null, all operand indices for Reg are added.
1463 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1464 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1465
1466 /// Return true if the MachineInstr kills the specified register.
1467 /// If TargetRegisterInfo is non-null, then it also checks if there is
1468 /// a kill of a super-register.
1470 const TargetRegisterInfo *TRI = nullptr) const {
1471 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1472 }
1473
1474 /// Return true if the MachineInstr fully defines the specified register.
1475 /// If TargetRegisterInfo is non-null, then it also checks
1476 /// if there is a def of a super-register.
1477 /// NOTE: It's ignoring subreg indices on virtual registers.
1479 const TargetRegisterInfo *TRI = nullptr) const {
1480 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1481 }
1482
1483 /// Return true if the MachineInstr modifies (fully define or partially
1484 /// define) the specified register.
1485 /// NOTE: It's ignoring subreg indices on virtual registers.
1487 const TargetRegisterInfo *TRI = nullptr) const {
1488 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1489 }
1490
1491 /// Returns true if the register is dead in this machine instruction.
1492 /// If TargetRegisterInfo is non-null, then it also checks
1493 /// if there is a dead def of a super-register.
1495 const TargetRegisterInfo *TRI = nullptr) const {
1496 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1497 }
1498
1499 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1500 /// the given register (not considering sub/super-registers).
1502
1503 /// Returns the operand index that is a use of the specific register or -1
1504 /// if it is not found. It further tightens the search criteria to a use
1505 /// that kills the register if isKill is true.
1506 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1507 const TargetRegisterInfo *TRI = nullptr) const;
1508
1509 /// Wrapper for findRegisterUseOperandIdx, it returns
1510 /// a pointer to the MachineOperand rather than an index.
1512 const TargetRegisterInfo *TRI = nullptr) {
1514 return (Idx == -1) ? nullptr : &getOperand(Idx);
1515 }
1516
1518 Register Reg, bool isKill = false,
1519 const TargetRegisterInfo *TRI = nullptr) const {
1520 return const_cast<MachineInstr *>(this)->
1522 }
1523
1524 /// Returns the operand index that is a def of the specified register or
1525 /// -1 if it is not found. If isDead is true, defs that are not dead are
1526 /// skipped. If Overlap is true, then it also looks for defs that merely
1527 /// overlap the specified register. If TargetRegisterInfo is non-null,
1528 /// then it also checks if there is a def of a super-register.
1529 /// This may also return a register mask operand when Overlap is true.
1531 bool isDead = false, bool Overlap = false,
1532 const TargetRegisterInfo *TRI = nullptr) const;
1533
1534 /// Wrapper for findRegisterDefOperandIdx, it returns
1535 /// a pointer to the MachineOperand rather than an index.
1538 bool Overlap = false,
1539 const TargetRegisterInfo *TRI = nullptr) {
1540 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1541 return (Idx == -1) ? nullptr : &getOperand(Idx);
1542 }
1543
1544 const MachineOperand *
1546 bool Overlap = false,
1547 const TargetRegisterInfo *TRI = nullptr) const {
1548 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1549 Reg, isDead, Overlap, TRI);
1550 }
1551
1552 /// Find the index of the first operand in the
1553 /// operand list that is used to represent the predicate. It returns -1 if
1554 /// none is found.
1555 int findFirstPredOperandIdx() const;
1556
1557 /// Find the index of the flag word operand that
1558 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1559 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1560 ///
1561 /// If GroupNo is not NULL, it will receive the number of the operand group
1562 /// containing OpIdx.
1563 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1564
1565 /// Compute the static register class constraint for operand OpIdx.
1566 /// For normal instructions, this is derived from the MCInstrDesc.
1567 /// For inline assembly it is derived from the flag words.
1568 ///
1569 /// Returns NULL if the static register class constraint cannot be
1570 /// determined.
1571 const TargetRegisterClass*
1572 getRegClassConstraint(unsigned OpIdx,
1573 const TargetInstrInfo *TII,
1574 const TargetRegisterInfo *TRI) const;
1575
1576 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1577 /// the given \p CurRC.
1578 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1579 /// instructions inside the bundle will be taken into account. In other words,
1580 /// this method accumulates all the constraints of the operand of this MI and
1581 /// the related bundle if MI is a bundle or inside a bundle.
1582 ///
1583 /// Returns the register class that satisfies both \p CurRC and the
1584 /// constraints set by MI. Returns NULL if such a register class does not
1585 /// exist.
1586 ///
1587 /// \pre CurRC must not be NULL.
1589 Register Reg, const TargetRegisterClass *CurRC,
1591 bool ExploreBundle = false) const;
1592
1593 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1594 /// to the given \p CurRC.
1595 ///
1596 /// Returns the register class that satisfies both \p CurRC and the
1597 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1598 /// does not exist.
1599 ///
1600 /// \pre CurRC must not be NULL.
1601 /// \pre The operand at \p OpIdx must be a register.
1602 const TargetRegisterClass *
1603 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1604 const TargetInstrInfo *TII,
1605 const TargetRegisterInfo *TRI) const;
1606
1607 /// Add a tie between the register operands at DefIdx and UseIdx.
1608 /// The tie will cause the register allocator to ensure that the two
1609 /// operands are assigned the same physical register.
1610 ///
1611 /// Tied operands are managed automatically for explicit operands in the
1612 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1613 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1614
1615 /// Given the index of a tied register operand, find the
1616 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1617 /// index of the tied operand which must exist.
1618 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1619
1620 /// Given the index of a register def operand,
1621 /// check if the register def is tied to a source operand, due to either
1622 /// two-address elimination or inline assembly constraints. Returns the
1623 /// first tied use operand index by reference if UseOpIdx is not null.
1624 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1625 unsigned *UseOpIdx = nullptr) const {
1626 const MachineOperand &MO = getOperand(DefOpIdx);
1627 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1628 return false;
1629 if (UseOpIdx)
1630 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1631 return true;
1632 }
1633
1634 /// Return true if the use operand of the specified index is tied to a def
1635 /// operand. It also returns the def operand index by reference if DefOpIdx
1636 /// is not null.
1637 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1638 unsigned *DefOpIdx = nullptr) const {
1639 const MachineOperand &MO = getOperand(UseOpIdx);
1640 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1641 return false;
1642 if (DefOpIdx)
1643 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1644 return true;
1645 }
1646
1647 /// Clears kill flags on all operands.
1648 void clearKillInfo();
1649
1650 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1651 /// properly composing subreg indices where necessary.
1652 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1654
1655 /// We have determined MI kills a register. Look for the
1656 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1657 /// add a implicit operand if it's not found. Returns true if the operand
1658 /// exists / is added.
1659 bool addRegisterKilled(Register IncomingReg,
1661 bool AddIfNotFound = false);
1662
1663 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1664 /// all aliasing registers.
1666
1667 /// We have determined MI defined a register without a use.
1668 /// Look for the operand that defines it and mark it as IsDead. If
1669 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1670 /// true if the operand exists / is added.
1672 bool AddIfNotFound = false);
1673
1674 /// Clear all dead flags on operands defining register @p Reg.
1676
1677 /// Mark all subregister defs of register @p Reg with the undef flag.
1678 /// This function is used when we determined to have a subregister def in an
1679 /// otherwise undefined super register.
1680 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1681
1682 /// We have determined MI defines a register. Make sure there is an operand
1683 /// defining Reg.
1685 const TargetRegisterInfo *RegInfo = nullptr);
1686
1687 /// Mark every physreg used by this instruction as
1688 /// dead except those in the UsedRegs list.
1689 ///
1690 /// On instructions with register mask operands, also add implicit-def
1691 /// operands for all registers in UsedRegs.
1693 const TargetRegisterInfo &TRI);
1694
1695 /// Return true if it is safe to move this instruction. If
1696 /// SawStore is set to true, it means that there is a store (or call) between
1697 /// the instruction's location and its intended destination.
1698 bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1699
1700 /// Returns true if this instruction's memory access aliases the memory
1701 /// access of Other.
1702 //
1703 /// Assumes any physical registers used to compute addresses
1704 /// have the same value for both instructions. Returns false if neither
1705 /// instruction writes to memory.
1706 ///
1707 /// @param AA Optional alias analysis, used to compare memory operands.
1708 /// @param Other MachineInstr to check aliasing against.
1709 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1710 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1711
1712 /// Return true if this instruction may have an ordered
1713 /// or volatile memory reference, or if the information describing the memory
1714 /// reference is not available. Return false if it is known to have no
1715 /// ordered or volatile memory references.
1716 bool hasOrderedMemoryRef() const;
1717
1718 /// Return true if this load instruction never traps and points to a memory
1719 /// location whose value doesn't change during the execution of this function.
1720 ///
1721 /// Examples include loading a value from the constant pool or from the
1722 /// argument area of a function (if it does not change). If the instruction
1723 /// does multiple loads, this returns true only if all of the loads are
1724 /// dereferenceable and invariant.
1725 bool isDereferenceableInvariantLoad() const;
1726
1727 /// If the specified instruction is a PHI that always merges together the
1728 /// same virtual register, return the register, otherwise return 0.
1729 unsigned isConstantValuePHI() const;
1730
1731 /// Return true if this instruction has side effects that are not modeled
1732 /// by mayLoad / mayStore, etc.
1733 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1734 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1735 /// INLINEASM instruction, in which case the side effect property is encoded
1736 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1737 ///
1738 bool hasUnmodeledSideEffects() const;
1739
1740 /// Returns true if it is illegal to fold a load across this instruction.
1741 bool isLoadFoldBarrier() const;
1742
1743 /// Return true if all the defs of this instruction are dead.
1744 bool allDefsAreDead() const;
1745
1746 /// Return true if all the implicit defs of this instruction are dead.
1747 bool allImplicitDefsAreDead() const;
1748
1749 /// Return a valid size if the instruction is a spill instruction.
1750 std::optional<LocationSize> getSpillSize(const TargetInstrInfo *TII) const;
1751
1752 /// Return a valid size if the instruction is a folded spill instruction.
1753 std::optional<LocationSize>
1755
1756 /// Return a valid size if the instruction is a restore instruction.
1757 std::optional<LocationSize> getRestoreSize(const TargetInstrInfo *TII) const;
1758
1759 /// Return a valid size if the instruction is a folded restore instruction.
1760 std::optional<LocationSize>
1762
1763 /// Copy implicit register operands from specified
1764 /// instruction to this instruction.
1766
1767 /// Debugging support
1768 /// @{
1769 /// Determine the generic type to be printed (if needed) on uses and defs.
1770 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1771 const MachineRegisterInfo &MRI) const;
1772
1773 /// Return true when an instruction has tied register that can't be determined
1774 /// by the instruction's descriptor. This is useful for MIR printing, to
1775 /// determine whether we need to print the ties or not.
1776 bool hasComplexRegisterTies() const;
1777
1778 /// Print this MI to \p OS.
1779 /// Don't print information that can be inferred from other instructions if
1780 /// \p IsStandalone is false. It is usually true when only a fragment of the
1781 /// function is printed.
1782 /// Only print the defs and the opcode if \p SkipOpers is true.
1783 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1784 /// Otherwise, also print the debug loc, with a terminating newline.
1785 /// \p TII is used to print the opcode name. If it's not present, but the
1786 /// MI is in a function, the opcode will be printed using the function's TII.
1787 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1788 bool SkipDebugLoc = false, bool AddNewLine = true,
1789 const TargetInstrInfo *TII = nullptr) const;
1790 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1791 bool SkipOpers = false, bool SkipDebugLoc = false,
1792 bool AddNewLine = true,
1793 const TargetInstrInfo *TII = nullptr) const;
1794 void dump() const;
1795 /// Print on dbgs() the current instruction and the instructions defining its
1796 /// operands and so on until we reach \p MaxDepth.
1797 void dumpr(const MachineRegisterInfo &MRI,
1798 unsigned MaxDepth = UINT_MAX) const;
1799 /// @}
1800
1801 //===--------------------------------------------------------------------===//
1802 // Accessors used to build up machine instructions.
1803
1804 /// Add the specified operand to the instruction. If it is an implicit
1805 /// operand, it is added to the end of the operand list. If it is an
1806 /// explicit operand it is added at the end of the explicit operand list
1807 /// (before the first implicit operand).
1808 ///
1809 /// MF must be the machine function that was used to allocate this
1810 /// instruction.
1811 ///
1812 /// MachineInstrBuilder provides a more convenient interface for creating
1813 /// instructions and adding operands.
1814 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1815
1816 /// Add an operand without providing an MF reference. This only works for
1817 /// instructions that are inserted in a basic block.
1818 ///
1819 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1820 /// preferred.
1821 void addOperand(const MachineOperand &Op);
1822
1823 /// Inserts Ops BEFORE It. Can untie/retie tied operands.
1824 void insert(mop_iterator InsertBefore, ArrayRef<MachineOperand> Ops);
1825
1826 /// Replace the instruction descriptor (thus opcode) of
1827 /// the current instruction with a new one.
1828 void setDesc(const MCInstrDesc &TID);
1829
1830 /// Replace current source information with new such.
1831 /// Avoid using this, the constructor argument is preferable.
1833 DbgLoc = std::move(DL);
1834 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1835 }
1836
1837 /// Erase an operand from an instruction, leaving it with one
1838 /// fewer operand than it started with.
1839 void removeOperand(unsigned OpNo);
1840
1841 /// Clear this MachineInstr's memory reference descriptor list. This resets
1842 /// the memrefs to their most conservative state. This should be used only
1843 /// as a last resort since it greatly pessimizes our knowledge of the memory
1844 /// access performed by the instruction.
1845 void dropMemRefs(MachineFunction &MF);
1846
1847 /// Assign this MachineInstr's memory reference descriptor list.
1848 ///
1849 /// Unlike other methods, this *will* allocate them into a new array
1850 /// associated with the provided `MachineFunction`.
1852
1853 /// Add a MachineMemOperand to the machine instruction.
1854 /// This function should be used only occasionally. The setMemRefs function
1855 /// is the primary method for setting up a MachineInstr's MemRefs list.
1857
1858 /// Clone another MachineInstr's memory reference descriptor list and replace
1859 /// ours with it.
1860 ///
1861 /// Note that `*this` may be the incoming MI!
1862 ///
1863 /// Prefer this API whenever possible as it can avoid allocations in common
1864 /// cases.
1865 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1866
1867 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1868 /// list and replace ours with it.
1869 ///
1870 /// Note that `*this` may be one of the incoming MIs!
1871 ///
1872 /// Prefer this API whenever possible as it can avoid allocations in common
1873 /// cases.
1876
1877 /// Set a symbol that will be emitted just prior to the instruction itself.
1878 ///
1879 /// Setting this to a null pointer will remove any such symbol.
1880 ///
1881 /// FIXME: This is not fully implemented yet.
1882 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1883
1884 /// Set a symbol that will be emitted just after the instruction itself.
1885 ///
1886 /// Setting this to a null pointer will remove any such symbol.
1887 ///
1888 /// FIXME: This is not fully implemented yet.
1889 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1890
1891 /// Clone another MachineInstr's pre- and post- instruction symbols and
1892 /// replace ours with it.
1894
1895 /// Set a marker on instructions that denotes where we should create and emit
1896 /// heap alloc site labels. This waits until after instruction selection and
1897 /// optimizations to create the label, so it should still work if the
1898 /// instruction is removed or duplicated.
1900
1901 // Set metadata on instructions that say which sections to emit instruction
1902 // addresses into.
1903 void setPCSections(MachineFunction &MF, MDNode *MD);
1904
1905 /// Set the CFI type for the instruction.
1907
1908 /// Return the MIFlags which represent both MachineInstrs. This
1909 /// should be used when merging two MachineInstrs into one. This routine does
1910 /// not modify the MIFlags of this MachineInstr.
1912
1914
1915 /// Copy all flags to MachineInst MIFlags
1916 void copyIRFlags(const Instruction &I);
1917
1918 /// Break any tie involving OpIdx.
1919 void untieRegOperand(unsigned OpIdx) {
1920 MachineOperand &MO = getOperand(OpIdx);
1921 if (MO.isReg() && MO.isTied()) {
1922 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1923 MO.TiedTo = 0;
1924 }
1925 }
1926
1927 /// Add all implicit def and use operands to this instruction.
1929
1930 /// Scan instructions immediately following MI and collect any matching
1931 /// DBG_VALUEs.
1933
1934 /// Find all DBG_VALUEs that point to the register def in this instruction
1935 /// and point them to \p Reg instead.
1937
1938 /// Sets all register debug operands in this debug value instruction to be
1939 /// undef.
1941 assert(isDebugValue() && "Must be a debug value instruction.");
1942 for (MachineOperand &MO : debug_operands()) {
1943 if (MO.isReg()) {
1944 MO.setReg(0);
1945 MO.setSubReg(0);
1946 }
1947 }
1948 }
1949
1950 std::tuple<Register, Register> getFirst2Regs() const {
1951 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg());
1952 }
1953
1954 std::tuple<Register, Register, Register> getFirst3Regs() const {
1955 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1956 getOperand(2).getReg());
1957 }
1958
1959 std::tuple<Register, Register, Register, Register> getFirst4Regs() const {
1960 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1961 getOperand(2).getReg(), getOperand(3).getReg());
1962 }
1963
1964 std::tuple<Register, Register, Register, Register, Register>
1966 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1968 getOperand(4).getReg());
1969 }
1970
1971 std::tuple<LLT, LLT> getFirst2LLTs() const;
1972 std::tuple<LLT, LLT, LLT> getFirst3LLTs() const;
1973 std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const;
1974 std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const;
1975
1976 std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const;
1977 std::tuple<Register, LLT, Register, LLT, Register, LLT>
1978 getFirst3RegLLTs() const;
1979 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
1980 getFirst4RegLLTs() const;
1981 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT,
1982 Register, LLT>
1983 getFirst5RegLLTs() const;
1984
1985private:
1986 /// If this instruction is embedded into a MachineFunction, return the
1987 /// MachineRegisterInfo object for the current function, otherwise
1988 /// return null.
1989 MachineRegisterInfo *getRegInfo();
1990 const MachineRegisterInfo *getRegInfo() const;
1991
1992 /// Unlink all of the register operands in this instruction from their
1993 /// respective use lists. This requires that the operands already be on their
1994 /// use lists.
1995 void removeRegOperandsFromUseLists(MachineRegisterInfo&);
1996
1997 /// Add all of the register operands in this instruction from their
1998 /// respective use lists. This requires that the operands not be on their
1999 /// use lists yet.
2000 void addRegOperandsToUseLists(MachineRegisterInfo&);
2001
2002 /// Slow path for hasProperty when we're dealing with a bundle.
2003 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
2004
2005 /// Implements the logic of getRegClassConstraintEffectForVReg for the
2006 /// this MI and the given operand index \p OpIdx.
2007 /// If the related operand does not constrained Reg, this returns CurRC.
2008 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
2009 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
2010 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
2011
2012 /// Stores extra instruction information inline or allocates as ExtraInfo
2013 /// based on the number of pointers.
2014 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
2015 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
2016 MDNode *HeapAllocMarker, MDNode *PCSections,
2017 uint32_t CFIType);
2018};
2019
2020/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
2021/// instruction rather than by pointer value.
2022/// The hashing and equality testing functions ignore definitions so this is
2023/// useful for CSE, etc.
2025 static inline MachineInstr *getEmptyKey() {
2026 return nullptr;
2027 }
2028
2030 return reinterpret_cast<MachineInstr*>(-1);
2031 }
2032
2033 static unsigned getHashValue(const MachineInstr* const &MI);
2034
2035 static bool isEqual(const MachineInstr* const &LHS,
2036 const MachineInstr* const &RHS) {
2037 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
2038 LHS == getEmptyKey() || LHS == getTombstoneKey())
2039 return LHS == RHS;
2040 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
2041 }
2042};
2043
2044//===----------------------------------------------------------------------===//
2045// Debugging Support
2046
2048 MI.print(OS);
2049 return OS;
2050}
2051
2052} // end namespace llvm
2053
2054#endif // LLVM_CODEGEN_MACHINEINSTR_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines DenseMapInfo traits for DenseMap.
#define Check(C,...)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static const unsigned MaxDepth
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
#define LLVM_MI_ASMPRINTERFLAGS_BITS
Definition: MachineInstr.h:131
#define LLVM_MI_FLAGS_BITS
Definition: MachineInstr.h:130
#define LLVM_MI_NUMOPERANDS_BITS
Definition: MachineInstr.h:129
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Promote Memory to Register
Definition: Mem2Reg.cpp:110
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
#define P(N)
Basic Register Allocator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
raw_pwrite_stream & OS
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This header defines support for implementing classes that have some trailing object (or arrays of obj...
Value * RHS
Value * LHS
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
DWARF expression.
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:251
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:579
unsigned short Opcode
Definition: MCInstrDesc.h:205
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Metadata node.
Definition: Metadata.h:1067
Representation of each machine instruction.
Definition: MachineInstr.h:69
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
mop_iterator operands_begin()
Definition: MachineInstr.h:656
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
std::tuple< Register, Register, Register, Register, Register > getFirst5Regs() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:546
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:628
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:908
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:587
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:576
bool isDebugValueList() const
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:717
void bundleWithPred()
Bundle this instruction with its predecessor.
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:77
bool isPosition() const
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:942
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
std::tuple< Register, Register, Register, Register > getFirst4Regs() const
bool isImplicitDef() const
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:714
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
bool isCopy() const
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:350
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:684
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:329
bool isCopyLike() const
Return true if the instruction behaves like a copy.
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
Definition: MachineInstr.h:532
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:842
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool isDebugOffsetImm() const
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:865
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
Definition: MachineInstr.h:392
MachineFunction * getMF()
Definition: MachineInstr.h:341
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:854
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:980
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:933
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
MachineBasicBlock * getParent()
Definition: MachineInstr.h:330
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:918
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:379
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:367
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:710
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:721
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
iterator_range< filtered_mop_iterator > all_uses()
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:743
bool isBundle() const
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:552
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:549
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:526
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:672
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
const MachineOperand * const_mop_iterator
Definition: MachineInstr.h:654
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:353
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool isInlineAsm() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:789
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:784
bool isDebugRef() const
bool isAnnotationLabel() const
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
MachineOperand & getDebugOffset()
Definition: MachineInstr.h:484
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:668
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:522
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:704
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:752
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isSubregToReg() const
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:987
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:620
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:950
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:454
bool isDebugPHI() const
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:560
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
const_mop_iterator operands_end() const
Definition: MachineInstr.h:660
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:360
bool isDebugOrPseudoInstr() const
bool isStackAligningInlineAsm() const
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
mop_iterator operands_end()
Definition: MachineInstr.h:657
bool isFullCopy() const
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:832
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:543
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
iterator_range< filtered_const_mop_iterator > all_uses() const
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:747
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
MachineInstr & operator=(const MachineInstr &)=delete
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:964
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:691
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:795
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:401
bool isGCLabel() const
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:347
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:633
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
bool isRegSequence() const
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:659
static uint32_t copyFlagsFromInstruction(const Instruction &I)
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MachineInstr.h:972
bool isJumpTableDebugInfo() const
std::tuple< Register, Register, Register > getFirst3Regs() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:792
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:662
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:999
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
const MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
bool isInsertSubreg() const
iterator_range< filtered_const_mop_iterator > all_defs() const
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:737
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
Definition: MachineInstr.h:600
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:699
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:777
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:442
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:665
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:759
bool isLabel() const
Returns true if the MachineInstr represents a label.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isExtractSubreg() const
bool isNonListDebugValue() const
MachineOperand * mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
Definition: MachineInstr.h:653
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:386
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:475
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MachineInstr.h:993
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
Definition: MachineInstr.h:878
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:914
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MachineInstr.h:898
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:679
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:798
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:892
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
bool isDebugValue() const
unsigned getDebugOperandIndex(const MachineOperand *Op) const
Definition: MachineInstr.h:609
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:480
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:565
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:676
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:458
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:822
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
bool isDebugOperand(const MachineOperand *Op) const
Definition: MachineInstr.h:605
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
bool isPHI() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:556
uint32_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:374
bool isEHLabel() const
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:810
void unbundleFromSucc()
Break bundle below this instruction.
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:733
const MachineOperand & getDebugOperand(unsigned Index) const
Definition: MachineInstr.h:569
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:615
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void setPCSections(MachineFunction &MF, MDNode *MD)
MachineInstr(const MachineInstr &)=delete
bool isKill() const
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isMetaInstruction(QueryType Type=IgnoreBundle) const
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition: MachineInstr.h:904
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
Definition: MachineInstr.h:594
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:956
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:886
const MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:448
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
std::tuple< Register, Register > getFirst2Regs() const
~MachineInstr()=delete
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Manage lifetime of a slot tracker for printing IR.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:321
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Specialization of filter_iterator_base for forward iteration only.
Definition: STLExtras.h:506
An ilist node that can access its parent list.
Definition: ilist_node.h:284
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This file defines classes to implement an intrusive doubly linked list class (i.e.
This file defines the ilist_node class template, which is a convenient base class for creating classe...
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:181
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:175
@ MayRaiseFPException
Definition: MCInstrDesc.h:170
@ Rematerializable
Definition: MCInstrDesc.h:178
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:180
@ UsesCustomInserter
Definition: MCInstrDesc.h:176
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
constexpr auto adl_begin(RangeT &&range) -> decltype(adl_detail::begin_impl(std::forward< RangeT >(range)))
Returns the begin iterator to range using std::begin and function found through Argument-Dependent Lo...
Definition: ADL.h:62
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
constexpr auto adl_end(RangeT &&range) -> decltype(adl_detail::end_impl(std::forward< RangeT >(range)))
Returns the end iterator to range using std::end and functions found through Argument-Dependent Looku...
Definition: ADL.h:70
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1738
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:581
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
Definition: Allocator.h:375
@ Other
Any other memory.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:293
ArrayRef(const T &OneElt) -> ArrayRef< T >
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: DenseMapInfo.h:50
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
static MachineInstr * getEmptyKey()
static unsigned getHashValue(const MachineInstr *const &MI)
static MachineInstr * getTombstoneKey()
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:65
Template traits for intrusive list.
Definition: ilist.h:90