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MachineRegisterInfo.h
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00001 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines the MachineRegisterInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
00015 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
00016 
00017 #include "llvm/ADT/BitVector.h"
00018 #include "llvm/ADT/IndexedMap.h"
00019 #include "llvm/CodeGen/MachineInstrBundle.h"
00020 #include "llvm/Target/TargetRegisterInfo.h"
00021 #include <vector>
00022 
00023 namespace llvm {
00024 
00025 /// MachineRegisterInfo - Keep track of information for virtual and physical
00026 /// registers, including vreg register classes, use/def chains for registers,
00027 /// etc.
00028 class MachineRegisterInfo {
00029   const TargetRegisterInfo *const TRI;
00030 
00031   /// IsSSA - True when the machine function is in SSA form and virtual
00032   /// registers have a single def.
00033   bool IsSSA;
00034 
00035   /// TracksLiveness - True while register liveness is being tracked accurately.
00036   /// Basic block live-in lists, kill flags, and implicit defs may not be
00037   /// accurate when after this flag is cleared.
00038   bool TracksLiveness;
00039 
00040   /// VRegInfo - Information we keep for each virtual register.
00041   ///
00042   /// Each element in this list contains the register class of the vreg and the
00043   /// start of the use/def list for the register.
00044   IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
00045              VirtReg2IndexFunctor> VRegInfo;
00046 
00047   /// RegAllocHints - This vector records register allocation hints for virtual
00048   /// registers. For each virtual register, it keeps a register and hint type
00049   /// pair making up the allocation hint. Hint type is target specific except
00050   /// for the value 0 which means the second value of the pair is the preferred
00051   /// register for allocation. For example, if the hint is <0, 1024>, it means
00052   /// the allocator should prefer the physical register allocated to the virtual
00053   /// register of the hint.
00054   IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
00055 
00056   /// PhysRegUseDefLists - This is an array of the head of the use/def list for
00057   /// physical registers.
00058   MachineOperand **PhysRegUseDefLists;
00059 
00060   /// getRegUseDefListHead - Return the head pointer for the register use/def
00061   /// list for the specified virtual or physical register.
00062   MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
00063     if (TargetRegisterInfo::isVirtualRegister(RegNo))
00064       return VRegInfo[RegNo].second;
00065     return PhysRegUseDefLists[RegNo];
00066   }
00067 
00068   MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
00069     if (TargetRegisterInfo::isVirtualRegister(RegNo))
00070       return VRegInfo[RegNo].second;
00071     return PhysRegUseDefLists[RegNo];
00072   }
00073 
00074   /// Get the next element in the use-def chain.
00075   static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
00076     assert(MO && MO->isReg() && "This is not a register operand!");
00077     return MO->Contents.Reg.Next;
00078   }
00079 
00080   /// UsedRegUnits - This is a bit vector that is computed and set by the
00081   /// register allocator, and must be kept up to date by passes that run after
00082   /// register allocation (though most don't modify this).  This is used
00083   /// so that the code generator knows which callee save registers to save and
00084   /// for other target specific uses.
00085   /// This vector has bits set for register units that are modified in the
00086   /// current function. It doesn't include registers clobbered by function
00087   /// calls with register mask operands.
00088   BitVector UsedRegUnits;
00089 
00090   /// UsedPhysRegMask - Additional used physregs including aliases.
00091   /// This bit vector represents all the registers clobbered by function calls.
00092   /// It can model things that UsedRegUnits can't, such as function calls that
00093   /// clobber ymm7 but preserve the low half in xmm7.
00094   BitVector UsedPhysRegMask;
00095 
00096   /// ReservedRegs - This is a bit vector of reserved registers.  The target
00097   /// may change its mind about which registers should be reserved.  This
00098   /// vector is the frozen set of reserved registers when register allocation
00099   /// started.
00100   BitVector ReservedRegs;
00101 
00102   /// Keep track of the physical registers that are live in to the function.
00103   /// Live in values are typically arguments in registers.  LiveIn values are
00104   /// allowed to have virtual registers associated with them, stored in the
00105   /// second element.
00106   std::vector<std::pair<unsigned, unsigned> > LiveIns;
00107 
00108   MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
00109   void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
00110 public:
00111   explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
00112   ~MachineRegisterInfo();
00113 
00114   //===--------------------------------------------------------------------===//
00115   // Function State
00116   //===--------------------------------------------------------------------===//
00117 
00118   // isSSA - Returns true when the machine function is in SSA form. Early
00119   // passes require the machine function to be in SSA form where every virtual
00120   // register has a single defining instruction.
00121   //
00122   // The TwoAddressInstructionPass and PHIElimination passes take the machine
00123   // function out of SSA form when they introduce multiple defs per virtual
00124   // register.
00125   bool isSSA() const { return IsSSA; }
00126 
00127   // leaveSSA - Indicates that the machine function is no longer in SSA form.
00128   void leaveSSA() { IsSSA = false; }
00129 
00130   /// tracksLiveness - Returns true when tracking register liveness accurately.
00131   ///
00132   /// While this flag is true, register liveness information in basic block
00133   /// live-in lists and machine instruction operands is accurate. This means it
00134   /// can be used to change the code in ways that affect the values in
00135   /// registers, for example by the register scavenger.
00136   ///
00137   /// When this flag is false, liveness is no longer reliable.
00138   bool tracksLiveness() const { return TracksLiveness; }
00139 
00140   /// invalidateLiveness - Indicates that register liveness is no longer being
00141   /// tracked accurately.
00142   ///
00143   /// This should be called by late passes that invalidate the liveness
00144   /// information.
00145   void invalidateLiveness() { TracksLiveness = false; }
00146 
00147   //===--------------------------------------------------------------------===//
00148   // Register Info
00149   //===--------------------------------------------------------------------===//
00150 
00151   // Strictly for use by MachineInstr.cpp.
00152   void addRegOperandToUseList(MachineOperand *MO);
00153 
00154   // Strictly for use by MachineInstr.cpp.
00155   void removeRegOperandFromUseList(MachineOperand *MO);
00156 
00157   // Strictly for use by MachineInstr.cpp.
00158   void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
00159 
00160   /// Verify the sanity of the use list for Reg.
00161   void verifyUseList(unsigned Reg) const;
00162 
00163   /// Verify the use list of all registers.
00164   void verifyUseLists() const;
00165 
00166   /// reg_begin/reg_end - Provide iteration support to walk over all definitions
00167   /// and uses of a register within the MachineFunction that corresponds to this
00168   /// MachineRegisterInfo object.
00169   template<bool Uses, bool Defs, bool SkipDebug>
00170   class defusechain_iterator;
00171 
00172   // Make it a friend so it can access getNextOperandForReg().
00173   template<bool, bool, bool> friend class defusechain_iterator;
00174 
00175   /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
00176   /// register.
00177   typedef defusechain_iterator<true,true,false> reg_iterator;
00178   reg_iterator reg_begin(unsigned RegNo) const {
00179     return reg_iterator(getRegUseDefListHead(RegNo));
00180   }
00181   static reg_iterator reg_end() { return reg_iterator(0); }
00182 
00183   /// reg_empty - Return true if there are no instructions using or defining the
00184   /// specified register (it may be live-in).
00185   bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
00186 
00187   /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
00188   /// of the specified register, skipping those marked as Debug.
00189   typedef defusechain_iterator<true,true,true> reg_nodbg_iterator;
00190   reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
00191     return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
00192   }
00193   static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
00194 
00195   /// reg_nodbg_empty - Return true if the only instructions using or defining
00196   /// Reg are Debug instructions.
00197   bool reg_nodbg_empty(unsigned RegNo) const {
00198     return reg_nodbg_begin(RegNo) == reg_nodbg_end();
00199   }
00200 
00201   /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
00202   typedef defusechain_iterator<false,true,false> def_iterator;
00203   def_iterator def_begin(unsigned RegNo) const {
00204     return def_iterator(getRegUseDefListHead(RegNo));
00205   }
00206   static def_iterator def_end() { return def_iterator(0); }
00207 
00208   /// def_empty - Return true if there are no instructions defining the
00209   /// specified register (it may be live-in).
00210   bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
00211 
00212   /// hasOneDef - Return true if there is exactly one instruction defining the
00213   /// specified register.
00214   bool hasOneDef(unsigned RegNo) const {
00215     def_iterator DI = def_begin(RegNo);
00216     if (DI == def_end())
00217       return false;
00218     return ++DI == def_end();
00219   }
00220 
00221   /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
00222   typedef defusechain_iterator<true,false,false> use_iterator;
00223   use_iterator use_begin(unsigned RegNo) const {
00224     return use_iterator(getRegUseDefListHead(RegNo));
00225   }
00226   static use_iterator use_end() { return use_iterator(0); }
00227 
00228   /// use_empty - Return true if there are no instructions using the specified
00229   /// register.
00230   bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
00231 
00232   /// hasOneUse - Return true if there is exactly one instruction using the
00233   /// specified register.
00234   bool hasOneUse(unsigned RegNo) const {
00235     use_iterator UI = use_begin(RegNo);
00236     if (UI == use_end())
00237       return false;
00238     return ++UI == use_end();
00239   }
00240 
00241   /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
00242   /// specified register, skipping those marked as Debug.
00243   typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
00244   use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
00245     return use_nodbg_iterator(getRegUseDefListHead(RegNo));
00246   }
00247   static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
00248 
00249   /// use_nodbg_empty - Return true if there are no non-Debug instructions
00250   /// using the specified register.
00251   bool use_nodbg_empty(unsigned RegNo) const {
00252     return use_nodbg_begin(RegNo) == use_nodbg_end();
00253   }
00254 
00255   /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
00256   /// instruction using the specified register.
00257   bool hasOneNonDBGUse(unsigned RegNo) const;
00258 
00259   /// replaceRegWith - Replace all instances of FromReg with ToReg in the
00260   /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
00261   /// except that it also changes any definitions of the register as well.
00262   ///
00263   /// Note that it is usually necessary to first constrain ToReg's register
00264   /// class to match the FromReg constraints using:
00265   ///
00266   ///   constrainRegClass(ToReg, getRegClass(FromReg))
00267   ///
00268   /// That function will return NULL if the virtual registers have incompatible
00269   /// constraints.
00270   void replaceRegWith(unsigned FromReg, unsigned ToReg);
00271 
00272   /// getVRegDef - Return the machine instr that defines the specified virtual
00273   /// register or null if none is found.  This assumes that the code is in SSA
00274   /// form, so there should only be one definition.
00275   MachineInstr *getVRegDef(unsigned Reg) const;
00276 
00277   /// getUniqueVRegDef - Return the unique machine instr that defines the
00278   /// specified virtual register or null if none is found.  If there are
00279   /// multiple definitions or no definition, return null.
00280   MachineInstr *getUniqueVRegDef(unsigned Reg) const;
00281 
00282   /// clearKillFlags - Iterate over all the uses of the given register and
00283   /// clear the kill flag from the MachineOperand. This function is used by
00284   /// optimization passes which extend register lifetimes and need only
00285   /// preserve conservative kill flag information.
00286   void clearKillFlags(unsigned Reg) const;
00287 
00288 #ifndef NDEBUG
00289   void dumpUses(unsigned RegNo) const;
00290 #endif
00291 
00292   /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
00293   /// throughout the function.  It is safe to move instructions that read such
00294   /// a physreg.
00295   bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
00296 
00297   //===--------------------------------------------------------------------===//
00298   // Virtual Register Info
00299   //===--------------------------------------------------------------------===//
00300 
00301   /// getRegClass - Return the register class of the specified virtual register.
00302   ///
00303   const TargetRegisterClass *getRegClass(unsigned Reg) const {
00304     return VRegInfo[Reg].first;
00305   }
00306 
00307   /// setRegClass - Set the register class of the specified virtual register.
00308   ///
00309   void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
00310 
00311   /// constrainRegClass - Constrain the register class of the specified virtual
00312   /// register to be a common subclass of RC and the current register class,
00313   /// but only if the new class has at least MinNumRegs registers.  Return the
00314   /// new register class, or NULL if no such class exists.
00315   /// This should only be used when the constraint is known to be trivial, like
00316   /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
00317   ///
00318   const TargetRegisterClass *constrainRegClass(unsigned Reg,
00319                                                const TargetRegisterClass *RC,
00320                                                unsigned MinNumRegs = 0);
00321 
00322   /// recomputeRegClass - Try to find a legal super-class of Reg's register
00323   /// class that still satisfies the constraints from the instructions using
00324   /// Reg.  Returns true if Reg was upgraded.
00325   ///
00326   /// This method can be used after constraints have been removed from a
00327   /// virtual register, for example after removing instructions or splitting
00328   /// the live range.
00329   ///
00330   bool recomputeRegClass(unsigned Reg, const TargetMachine&);
00331 
00332   /// createVirtualRegister - Create and return a new virtual register in the
00333   /// function with the specified register class.
00334   ///
00335   unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
00336 
00337   /// getNumVirtRegs - Return the number of virtual registers created.
00338   ///
00339   unsigned getNumVirtRegs() const { return VRegInfo.size(); }
00340 
00341   /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
00342   void clearVirtRegs();
00343 
00344   /// setRegAllocationHint - Specify a register allocation hint for the
00345   /// specified virtual register.
00346   void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
00347     RegAllocHints[Reg].first  = Type;
00348     RegAllocHints[Reg].second = PrefReg;
00349   }
00350 
00351   /// getRegAllocationHint - Return the register allocation hint for the
00352   /// specified virtual register.
00353   std::pair<unsigned, unsigned>
00354   getRegAllocationHint(unsigned Reg) const {
00355     return RegAllocHints[Reg];
00356   }
00357 
00358   /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
00359   /// standard simple hint (Type == 0) is not set.
00360   unsigned getSimpleHint(unsigned Reg) const {
00361     std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
00362     return Hint.first ? 0 : Hint.second;
00363   }
00364 
00365 
00366   //===--------------------------------------------------------------------===//
00367   // Physical Register Use Info
00368   //===--------------------------------------------------------------------===//
00369 
00370   /// isPhysRegUsed - Return true if the specified register is used in this
00371   /// function. Also check for clobbered aliases and registers clobbered by
00372   /// function calls with register mask operands.
00373   ///
00374   /// This only works after register allocation. It is primarily used by
00375   /// PrologEpilogInserter to determine which callee-saved registers need
00376   /// spilling.
00377   bool isPhysRegUsed(unsigned Reg) const {
00378     if (UsedPhysRegMask.test(Reg))
00379       return true;
00380     for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
00381       if (UsedRegUnits.test(*Units))
00382         return true;
00383     return false;
00384   }
00385 
00386   /// Mark the specified register unit as used in this function.
00387   /// This should only be called during and after register allocation.
00388   void setRegUnitUsed(unsigned RegUnit) {
00389     UsedRegUnits.set(RegUnit);
00390   }
00391 
00392   /// setPhysRegUsed - Mark the specified register used in this function.
00393   /// This should only be called during and after register allocation.
00394   void setPhysRegUsed(unsigned Reg) {
00395     for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
00396       UsedRegUnits.set(*Units);
00397   }
00398 
00399   /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
00400   /// This corresponds to the bit mask attached to register mask operands.
00401   void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
00402     UsedPhysRegMask.setBitsNotInMask(RegMask);
00403   }
00404 
00405   /// setPhysRegUnused - Mark the specified register unused in this function.
00406   /// This should only be called during and after register allocation.
00407   void setPhysRegUnused(unsigned Reg) {
00408     UsedPhysRegMask.reset(Reg);
00409     for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
00410       UsedRegUnits.reset(*Units);
00411   }
00412 
00413 
00414   //===--------------------------------------------------------------------===//
00415   // Reserved Register Info
00416   //===--------------------------------------------------------------------===//
00417   //
00418   // The set of reserved registers must be invariant during register
00419   // allocation.  For example, the target cannot suddenly decide it needs a
00420   // frame pointer when the register allocator has already used the frame
00421   // pointer register for something else.
00422   //
00423   // These methods can be used by target hooks like hasFP() to avoid changing
00424   // the reserved register set during register allocation.
00425 
00426   /// freezeReservedRegs - Called by the register allocator to freeze the set
00427   /// of reserved registers before allocation begins.
00428   void freezeReservedRegs(const MachineFunction&);
00429 
00430   /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
00431   /// to ensure the set of reserved registers stays constant.
00432   bool reservedRegsFrozen() const {
00433     return !ReservedRegs.empty();
00434   }
00435 
00436   /// canReserveReg - Returns true if PhysReg can be used as a reserved
00437   /// register.  Any register can be reserved before freezeReservedRegs() is
00438   /// called.
00439   bool canReserveReg(unsigned PhysReg) const {
00440     return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
00441   }
00442 
00443   /// getReservedRegs - Returns a reference to the frozen set of reserved
00444   /// registers. This method should always be preferred to calling
00445   /// TRI::getReservedRegs() when possible.
00446   const BitVector &getReservedRegs() const {
00447     assert(reservedRegsFrozen() &&
00448            "Reserved registers haven't been frozen yet. "
00449            "Use TRI::getReservedRegs().");
00450     return ReservedRegs;
00451   }
00452 
00453   /// isReserved - Returns true when PhysReg is a reserved register.
00454   ///
00455   /// Reserved registers may belong to an allocatable register class, but the
00456   /// target has explicitly requested that they are not used.
00457   ///
00458   bool isReserved(unsigned PhysReg) const {
00459     return getReservedRegs().test(PhysReg);
00460   }
00461 
00462   /// isAllocatable - Returns true when PhysReg belongs to an allocatable
00463   /// register class and it hasn't been reserved.
00464   ///
00465   /// Allocatable registers may show up in the allocation order of some virtual
00466   /// register, so a register allocator needs to track its liveness and
00467   /// availability.
00468   bool isAllocatable(unsigned PhysReg) const {
00469     return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
00470   }
00471 
00472   //===--------------------------------------------------------------------===//
00473   // LiveIn Management
00474   //===--------------------------------------------------------------------===//
00475 
00476   /// addLiveIn - Add the specified register as a live-in.  Note that it
00477   /// is an error to add the same register to the same set more than once.
00478   void addLiveIn(unsigned Reg, unsigned vreg = 0) {
00479     LiveIns.push_back(std::make_pair(Reg, vreg));
00480   }
00481 
00482   // Iteration support for the live-ins set.  It's kept in sorted order
00483   // by register number.
00484   typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
00485   livein_iterator;
00486   livein_iterator livein_begin() const { return LiveIns.begin(); }
00487   livein_iterator livein_end()   const { return LiveIns.end(); }
00488   bool            livein_empty() const { return LiveIns.empty(); }
00489 
00490   bool isLiveIn(unsigned Reg) const;
00491 
00492   /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
00493   /// corresponding live-in physical register.
00494   unsigned getLiveInPhysReg(unsigned VReg) const;
00495 
00496   /// getLiveInVirtReg - If PReg is a live-in physical register, return the
00497   /// corresponding live-in physical register.
00498   unsigned getLiveInVirtReg(unsigned PReg) const;
00499 
00500   /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
00501   /// into the given entry block.
00502   void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
00503                         const TargetRegisterInfo &TRI,
00504                         const TargetInstrInfo &TII);
00505 
00506   /// defusechain_iterator - This class provides iterator support for machine
00507   /// operands in the function that use or define a specific register.  If
00508   /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
00509   /// returns defs.  If neither are true then you are silly and it always
00510   /// returns end().  If SkipDebug is true it skips uses marked Debug
00511   /// when incrementing.
00512   template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
00513   class defusechain_iterator
00514     : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
00515     MachineOperand *Op;
00516     explicit defusechain_iterator(MachineOperand *op) : Op(op) {
00517       // If the first node isn't one we're interested in, advance to one that
00518       // we are interested in.
00519       if (op) {
00520         if ((!ReturnUses && op->isUse()) ||
00521             (!ReturnDefs && op->isDef()) ||
00522             (SkipDebug && op->isDebug()))
00523           ++*this;
00524       }
00525     }
00526     friend class MachineRegisterInfo;
00527   public:
00528     typedef std::iterator<std::forward_iterator_tag,
00529                           MachineInstr, ptrdiff_t>::reference reference;
00530     typedef std::iterator<std::forward_iterator_tag,
00531                           MachineInstr, ptrdiff_t>::pointer pointer;
00532 
00533     defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
00534     defusechain_iterator() : Op(0) {}
00535 
00536     bool operator==(const defusechain_iterator &x) const {
00537       return Op == x.Op;
00538     }
00539     bool operator!=(const defusechain_iterator &x) const {
00540       return !operator==(x);
00541     }
00542 
00543     /// atEnd - return true if this iterator is equal to reg_end() on the value.
00544     bool atEnd() const { return Op == 0; }
00545 
00546     // Iterator traversal: forward iteration only
00547     defusechain_iterator &operator++() {          // Preincrement
00548       assert(Op && "Cannot increment end iterator!");
00549       Op = getNextOperandForReg(Op);
00550 
00551       // All defs come before the uses, so stop def_iterator early.
00552       if (!ReturnUses) {
00553         if (Op) {
00554           if (Op->isUse())
00555             Op = 0;
00556           else
00557             assert(!Op->isDebug() && "Can't have debug defs");
00558         }
00559       } else {
00560         // If this is an operand we don't care about, skip it.
00561         while (Op && ((!ReturnDefs && Op->isDef()) ||
00562                       (SkipDebug && Op->isDebug())))
00563           Op = getNextOperandForReg(Op);
00564       }
00565 
00566       return *this;
00567     }
00568     defusechain_iterator operator++(int) {        // Postincrement
00569       defusechain_iterator tmp = *this; ++*this; return tmp;
00570     }
00571 
00572     /// skipInstruction - move forward until reaching a different instruction.
00573     /// Return the skipped instruction that is no longer pointed to, or NULL if
00574     /// already pointing to end().
00575     MachineInstr *skipInstruction() {
00576       if (!Op) return 0;
00577       MachineInstr *MI = Op->getParent();
00578       do ++*this;
00579       while (Op && Op->getParent() == MI);
00580       return MI;
00581     }
00582 
00583     MachineInstr *skipBundle() {
00584       if (!Op) return 0;
00585       MachineInstr *MI = getBundleStart(Op->getParent());
00586       do ++*this;
00587       while (Op && getBundleStart(Op->getParent()) == MI);
00588       return MI;
00589     }
00590 
00591     MachineOperand &getOperand() const {
00592       assert(Op && "Cannot dereference end iterator!");
00593       return *Op;
00594     }
00595 
00596     /// getOperandNo - Return the operand # of this MachineOperand in its
00597     /// MachineInstr.
00598     unsigned getOperandNo() const {
00599       assert(Op && "Cannot dereference end iterator!");
00600       return Op - &Op->getParent()->getOperand(0);
00601     }
00602 
00603     // Retrieve a reference to the current operand.
00604     MachineInstr &operator*() const {
00605       assert(Op && "Cannot dereference end iterator!");
00606       return *Op->getParent();
00607     }
00608 
00609     MachineInstr *operator->() const {
00610       assert(Op && "Cannot dereference end iterator!");
00611       return Op->getParent();
00612     }
00613   };
00614 
00615 };
00616 
00617 } // End llvm namespace
00618 
00619 #endif