81 TRI = MF->getSubtarget().getRegisterInfo();
82 MRI = &MF->getRegInfo();
83 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
84 TII = MF->getSubtarget().getInstrInfo();
100 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
101 DbgLoc(
std::
move(
DL)), DebugInstrNum(0) {
107 CapOperands = OperandCapacity::get(NumOps);
119 : MCID(&
MI.
getDesc()), NumOperands(0),
Flags(0), AsmPrinterFlags(0),
123 CapOperands = OperandCapacity::get(
MI.getNumOperands());
135 NewMO.TiedTo = OrigMO.TiedTo;
170 MRI.removeRegOperandFromUseList(&MO);
176 MRI.addRegOperandToUseList(&MO);
181 assert(
MBB &&
"Use MachineInstrBuilder to add operands to dangling instrs");
183 assert(MF &&
"Use MachineInstrBuilder to add operands to dangling instrs");
192 return MRI->moveOperands(Dst, Src, NumOps);
194 assert(Dst && Src &&
"Unknown operands");
203 assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&
204 "Cannot add more operands.");
205 assert(MCID &&
"Cannot add operands before providing an instr descriptor");
208 if (&
Op >= Operands && &
Op < Operands + NumOperands) {
224 bool isImpReg =
Op.isReg() &&
Op.isImplicit();
226 while (OpNo && Operands[OpNo-1].
isReg() && Operands[OpNo-1].isImplicit()) {
228 assert(!Operands[OpNo].isTied() &&
"Cannot move tied operands");
239 OperandCapacity OldCap = CapOperands;
242 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
250 if (OpNo != NumOperands)
251 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
256 if (OldOperands != Operands && OldOperands)
261 NewMO->ParentMI =
this;
264 if (NewMO->
isReg()) {
266 NewMO->Contents.Reg.Prev =
nullptr;
271 MRI->addRegOperandToUseList(NewMO);
277 if (NewMO->
isUse()) {
299 if (Operands[i].
isReg())
300 assert(!Operands[i].isTied() &&
"Cannot move tied operands");
305 MRI->removeRegOperandFromUseList(Operands + OpNo);
311 if (
unsigned N = NumOperands - 1 - OpNo)
322 bool HasPreInstrSymbol = PreInstrSymbol !=
nullptr;
323 bool HasPostInstrSymbol = PostInstrSymbol !=
nullptr;
324 bool HasHeapAllocMarker = HeapAllocMarker !=
nullptr;
325 bool HasPCSections = PCSections !=
nullptr;
326 bool HasCFIType = CFIType != 0;
327 int NumPointers = MMOs.
size() + HasPreInstrSymbol + HasPostInstrSymbol +
328 HasHeapAllocMarker + HasPCSections + HasCFIType;
331 if (NumPointers <= 0) {
340 else if (NumPointers > 1 || HasHeapAllocMarker || HasPCSections ||
342 Info.set<EIIK_OutOfLine>(
344 HeapAllocMarker, PCSections, CFIType));
349 if (HasPreInstrSymbol)
350 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
351 else if (HasPostInstrSymbol)
352 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
354 Info.set<EIIK_MMO>(MMOs[0]);
390 "Invalid machine functions when cloning memory refrences!");
410 if (
LHS.size() !=
RHS.size())
415 return std::equal(LHSPointees.begin(), LHSPointees.end(),
416 RHSPointees.begin());
426 if (MIs.
size() == 1) {
442 "Invalid machine functions when cloning memory references!");
447 "Invalid machine functions when cloning memory references!");
458 if (
MI.memoperands_empty()) {
464 MergedMMOs.
append(
MI.memoperands_begin(),
MI.memoperands_end());
476 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
491 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
534 "Invalid machine functions when cloning instruction symbols!");
552 dyn_cast<OverflowingBinaryOperator>(&
I)) {
553 if (OB->hasNoSignedWrap())
555 if (OB->hasNoUnsignedWrap())
557 }
else if (
const TruncInst *TI = dyn_cast<TruncInst>(&
I)) {
558 if (TI->hasNoSignedWrap())
560 if (TI->hasNoUnsignedWrap())
566 if (PNI->hasNonNeg())
570 dyn_cast<PossiblyDisjointInst>(&
I)) {
571 if (PD->isDisjoint())
587 if (Flags.noSignedZeros())
589 if (Flags.allowReciprocal())
591 if (Flags.allowContract())
593 if (Flags.approxFunc())
595 if (Flags.allowReassoc())
599 if (
I.getMetadata(LLVMContext::MD_unpredictable))
609bool MachineInstr::hasPropertyInBundle(
uint64_t Mask, QueryType
Type)
const {
612 if (MII->getDesc().getFlags() & Mask) {
620 if (!MII->isBundledWithSucc())
637 assert(
Other.isBundle() &&
"Expected that both instructions are bundles.");
642 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
645 if (!I1->isIdenticalTo(*I2,
Check))
650 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
718 Other.getDebugExpression(),
Other.isIndirectDebugValue()))
751 case TargetOpcode::PATCHPOINT:
752 case TargetOpcode::STACKMAP:
753 case TargetOpcode::STATEPOINT:
754 case TargetOpcode::FENTRY_CALL:
804 assert(!Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
813 assert(!Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
822 assert(Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
831 assert(Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
851 unsigned *GroupNo)
const {
868 NumOps = 1 +
F.getNumOperandRegisters();
869 if (i + NumOps > OpIdx) {
881 return cast<DILabel>(
getOperand(0).getMetadata());
925 assert(
getMF() &&
"Can't have an MF reference here!");
947 if ((
F.isRegUseKind() ||
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind()) &&
948 F.hasRegClassConstraint(RCID))
949 return TRI->getRegClass(RCID);
953 return TRI->getPointerRegClass(MF);
966 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
967 OpndIt.getOperandNo(), Reg, CurRC,
TII,
TRI);
970 for (
unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
971 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC,
TII,
TRI);
978 assert(CurRC &&
"Invalid initial register class");
993 "Cannot get register constraints for non-register operand");
994 assert(CurRC &&
"Invalid initial register class");
997 CurRC =
TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
999 CurRC =
TRI->getSubClassWithSubReg(CurRC, SubIdx);
1001 CurRC =
TRI->getCommonSubClass(CurRC, OpRC);
1010 while (
I->isBundledWithSucc()) {
1040 if (MOReg == Reg || (
TRI && Reg && MOReg &&
TRI->regsOverlap(MOReg, Reg)))
1053 bool PartDef =
false;
1054 bool FullDef =
false;
1072 return std::make_pair(
Use || (PartDef && !FullDef), PartDef || FullDef);
1082 bool isPhys = Reg.isPhysical();
1092 bool Found = (MOReg == Reg);
1095 Found =
TRI->regsOverlap(MOReg, Reg);
1097 Found =
TRI->isSubRegister(MOReg, Reg);
1099 if (Found && (!isDead || MO.
isDead()))
1116 if (MCID.
operands()[i].isPredicate())
1141 assert(DefMO.
isDef() &&
"DefIdx must be a def operand");
1142 assert(UseMO.
isUse() &&
"UseIdx must be a use operand");
1143 assert(!DefMO.
isTied() &&
"Def is already tied to another use");
1144 assert(!UseMO.
isTied() &&
"Use is already tied to another def");
1147 UseMO.TiedTo = DefIdx + 1;
1154 "DefIdx out of range");
1159 DefMO.TiedTo = std::min(UseIdx + 1,
TiedMax);
1171 return MO.TiedTo - 1;
1181 if (UseMO.
isReg() && UseMO.
isUse() && UseMO.TiedTo == OpIdx + 1)
1187 if (
getOpcode() == TargetOpcode::STATEPOINT) {
1192 assert(CurUseIdx != -1U &&
"only gc pointer statepoint operands can be tied");
1194 for (
unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1197 if (OpIdx == CurDefIdx)
1199 if (OpIdx == CurUseIdx)
1209 unsigned OpIdxGroup = ~0u;
1214 assert(FlagMO.
isImm() &&
"Invalid tied operand on inline asm");
1215 unsigned CurGroup = GroupIdx.
size();
1218 NumOps = 1 +
F.getNumOperandRegisters();
1220 if (OpIdx > i && OpIdx < i + NumOps)
1221 OpIdxGroup = CurGroup;
1223 if (!
F.isUseOperandTiedToDef(TiedGroup))
1227 unsigned Delta = i - GroupIdx[TiedGroup];
1230 if (OpIdxGroup == CurGroup)
1231 return OpIdx - Delta;
1234 if (OpIdxGroup == TiedGroup)
1235 return OpIdx + Delta;
1254 ToReg = RegInfo.
getSubReg(ToReg, SubIdx);
1320 int64_t MinOffset = std::min(OffsetA, OffsetB);
1324 bool KnownWidthA = WidthA.
hasValue();
1325 bool KnownWidthB = WidthB.
hasValue();
1330 bool SameVal = (ValA && ValB && (ValA == ValB));
1334 if (PSVa && ValB && !PSVa->
mayAlias(&MFI))
1336 if (PSVb && ValA && !PSVb->
mayAlias(&MFI))
1338 if (PSVa && PSVb && (PSVa == PSVb))
1342 if (SameVal && BothMMONonScalable) {
1343 if (!KnownWidthA || !KnownWidthB)
1345 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1346 int64_t LowWidth = (MinOffset == OffsetA)
1349 return (MinOffset + LowWidth > MaxOffset);
1358 assert((OffsetA >= 0) &&
"Negative MachineMemOperand offset");
1359 assert((OffsetB >= 0) &&
"Negative MachineMemOperand offset");
1417 if (NumChecks >
TII->getMemOperandAACheckLimit())
1423 for (
auto *MMOb :
Other.memoperands())
1469 if (!MMO->isUnordered())
1474 if (MMO->isStore())
return false;
1475 if (MMO->isInvariant() && MMO->isDereferenceable())
1480 if (PSV->isConstant(&MFI))
1499 "It's illegal to have a PHI without source operands");
1559 if (MCID.
Opcode == TargetOpcode::STATEPOINT)
1563 if (!Operand.isReg() || Operand.isDef())
1568 if (ExpectedTiedIdx != TiedIdx)
1581 return MRI.getType(
Op.getReg());
1584 if (!OpInfo.isGenericType())
1585 return MRI.getType(
Op.getReg());
1587 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1590 LLT TypeToPrint =
MRI.getType(
Op.getReg());
1594 PrintedTypes.
set(OpInfo.getGenericTypeIndex());
1598#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1609 if (!AlreadySeenInstrs.
insert(
this).second)
1620 if (Reg.isPhysical())
1623 if (NewMI ==
nullptr)
1637 bool SkipDebugLoc,
bool AddNewLine,
1639 const Module *M =
nullptr;
1651 print(
OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine,
TII);
1655 bool IsStandalone,
bool SkipOpers,
bool SkipDebugLoc,
1668 auto getTiedOperandIdx = [&](
unsigned OpIdx) {
1669 if (!ShouldPrintRegisterTies)
1676 unsigned StartOp = 0;
1680 while (StartOp < e) {
1689 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1690 MO.
print(
OS, MST, TypeToPrint, StartOp,
false, IsStandalone,
1691 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1699 OS <<
"frame-setup ";
1701 OS <<
"frame-destroy ";
1723 OS <<
"nofpexcept ";
1741 bool FirstOp =
true;
1742 unsigned AsmDescOp = ~0u;
1743 unsigned AsmOpCount = 0;
1750 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1752 ShouldPrintRegisterTies, TiedOperandIdx,
TRI,
1758 OS <<
" [sideeffect]";
1762 OS <<
" [maystore]";
1764 OS <<
" [isconvergent]";
1766 OS <<
" [alignstack]";
1768 OS <<
" [attdialect]";
1770 OS <<
" [inteldialect]";
1779 if (FirstOp) FirstOp =
false;
else OS <<
",";
1784 auto *DIV = dyn_cast<DILocalVariable>(MO.
getMetadata());
1785 if (DIV && !DIV->getName().empty())
1786 OS <<
"!\"" << DIV->getName() <<
'\"';
1789 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1790 MO.
print(
OS, MST, TypeToPrint, i,
true, IsStandalone,
1791 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1796 if (DIL && !DIL->getName().empty())
1797 OS <<
"\"" << DIL->getName() <<
'\"';
1800 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1801 MO.
print(
OS, MST, TypeToPrint, i,
true, IsStandalone,
1802 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1804 }
else if (i == AsmDescOp && MO.
isImm()) {
1806 OS <<
'$' << AsmOpCount++;
1807 unsigned Flag = MO.
getImm();
1810 OS <<
F.getKindName();
1813 if (!
F.isImmKind() && !
F.isMemKind() &&
F.hasRegClassConstraint(RCID)) {
1815 OS <<
':' <<
TRI->getRegClassName(
TRI->getRegClass(RCID));
1817 OS <<
":RC" << RCID;
1820 if (
F.isMemKind()) {
1826 if (
F.isUseOperandTiedToDef(TiedTo))
1827 OS <<
" tiedto:$" << TiedTo;
1829 if ((
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind() ||
1830 F.isRegUseKind()) &&
1831 F.getRegMayBeFolded()) {
1838 AsmDescOp += 1 +
F.getNumOperandRegisters();
1841 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1845 MO.
print(
OS, MST, TypeToPrint, i,
true, IsStandalone,
1846 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1857 OS <<
" pre-instr-symbol ";
1865 OS <<
" post-instr-symbol ";
1873 OS <<
" heap-alloc-marker ";
1881 OS <<
" pcsections ";
1887 OS <<
" cfi-type " << CFIType;
1890 if (DebugInstrNum) {
1893 OS <<
" debug-instr-number " << DebugInstrNum;
1896 if (!SkipDebugLoc) {
1900 OS <<
" debug-location ";
1908 std::unique_ptr<LLVMContext> CtxPtr;
1914 CtxPtr = std::make_unique<LLVMContext>();
1919 bool NeedComma =
false;
1931 bool HaveSemi =
false;
1953 OS <<
" line no:" << DV->getLine();
1966 bool AddIfNotFound) {
1968 bool hasAliases = isPhysReg &&
1987 if (Reg == IncomingReg) {
1998 }
else if (hasAliases && MO.
isKill() && Reg.isPhysical()) {
2008 while (!DeadOps.
empty()) {
2009 unsigned OpIdx = DeadOps.
back();
2020 if (!Found && AddIfNotFound) {
2032 if (!Reg.isPhysical())
2038 if ((RegInfo && RegInfo->
regsOverlap(Reg, OpReg)) || Reg == OpReg)
2045 bool AddIfNotFound) {
2046 bool isPhysReg = Reg.isPhysical();
2047 bool hasAliases = isPhysReg &&
2072 while (!DeadOps.
empty()) {
2073 unsigned OpIdx = DeadOps.
back();
2084 if (Found || !AddIfNotFound)
2113 if (Reg.isPhysical()) {
2131 bool HasRegMask =
false;
2139 if (!Reg.isPhysical())
2150 for (
const Register &UsedReg : UsedRegs)
2158 HashComponents.
reserve(
MI->getNumOperands() + 1);
2172 const MDNode *LocMD =
nullptr;
2178 mdconst::dyn_extract<ConstantInt>(LocMD->
getOperand(0))) {
2179 LocCookie = CI->getZExtValue();
2195 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2196 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2197 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
2198 "Expected inlined-at fields to agree");
2211 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2212 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2213 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
2214 "Expected inlined-at fields to agree");
2215 if (MCID.
Opcode == TargetOpcode::DBG_VALUE) {
2217 "DBG_VALUE must contain exactly one debug operand");
2219 if (DebugOp.
isReg())
2232 MIB.addMetadata(Variable).addMetadata(Expr);
2234 if (DebugOp.isReg())
2235 MIB.addReg(DebugOp.getReg());
2260 BuildMI(MF,
DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2270 assert(
MI.getDebugVariable()->isValidLocationForIntrinsic(
MI.getDebugLoc()) &&
2271 "Expected inlined-at fields to agree");
2274 if (
MI.isIndirectDebugValue()) {
2275 assert(
MI.getDebugOffset().getImm() == 0 &&
2276 "DBG_VALUE with nonzero offset");
2278 }
else if (
MI.isDebugValueList()) {
2281 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2283 unsigned OpIdx =
MI.getDebugOperandIndex(
Op);
2291 assert(
MI.hasDebugOperandForReg(SpillReg) &&
"Spill Reg is not used in MI.");
2301 int FrameIndex,
Register SpillReg) {
2303 "DBG_INSTR_REF should not reference a virtual register.");
2314 if (
Op.isReg() &&
Op.getReg() == SpillReg)
2349 Op.ChangeToFrameIndex(FrameIndex);
2356 if (!
MI.getOperand(0).isReg())
2362 if (!DI->isDebugValue())
2364 if (DI->hasDebugOperandForReg(
MI.getOperand(0).getReg()))
2377 auto *
MRI = getRegInfo();
2378 for (
auto &MO :
MRI->use_operands(DefReg)) {
2380 if (!DI->isDebugValue())
2382 if (DI->hasDebugOperandForReg(DefReg)) {
2388 for (
auto *DBI : DbgValues)
2398 for (
const auto *
A : Accesses) {
2400 cast<FixedStackPseudoSourceValue>(
A->getPseudoValue())
2401 ->getFrameIndex())) {
2411std::optional<LocationSize>
2414 if (
TII->isStoreToStackSlotPostFE(*
this, FI)) {
2419 return std::nullopt;
2422std::optional<LocationSize>
2427 return std::nullopt;
2430std::optional<LocationSize>
2433 if (
TII->isLoadFromStackSlotPostFE(*
this, FI)) {
2438 return std::nullopt;
2441std::optional<LocationSize>
2446 return std::nullopt;
2450 if (DebugInstrNum == 0)
2452 return DebugInstrNum;
2456 if (DebugInstrNum == 0)
2458 return DebugInstrNum;
2487std::tuple<Register, LLT, Register, LLT>
2491 return std::tuple(Reg0, getRegInfo()->
getType(Reg0), Reg1,
2495std::tuple<Register, LLT, Register, LLT, Register, LLT>
2500 return std::tuple(Reg0, getRegInfo()->
getType(Reg0), Reg1,
2501 getRegInfo()->
getType(Reg1), Reg2,
2505std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2512 Reg0, getRegInfo()->
getType(Reg0), Reg1, getRegInfo()->
getType(Reg1),
2513 Reg2, getRegInfo()->
getType(Reg2), Reg3, getRegInfo()->
getType(Reg3));
2525 Reg0, getRegInfo()->
getType(Reg0), Reg1, getRegInfo()->
getType(Reg1),
2526 Reg2, getRegInfo()->
getType(Reg2), Reg3, getRegInfo()->
getType(Reg3),
2527 Reg4, getRegInfo()->
getType(Reg4));
2532 assert(InsertBefore !=
nullptr &&
"invalid iterator");
2534 "iterator points to operand of other inst");
2544 TiedOpIndices[OpNo] = TiedTo;
2551 unsigned OpsToMove = NumOperands - OpIdx;
2556 for (
unsigned I = 0;
I < OpsToMove; ++
I) {
2566 for (
auto [Tie1, Tie2] : TiedOpIndices) {
2576 assert(OpId &&
"expected non-zero operand id");
2587 if (
F.isRegUseKind() ||
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind())
2588 return F.getRegMayBeFolded();
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const HexagonInstrInfo * TII
static const unsigned MaxDepth
Implement a low-level type suitable for MachineInstr level instruction selection.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
static LocationSize getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
Module.h This file contains the declarations for the Module class.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This file implements the SmallBitVector class.
This file defines the SmallVector class.
static SymbolRef::Type getType(const Symbol *Sym)
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect)
Determines whether two debug values should produce equivalent DWARF expressions, using their DIExpres...
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Utility class for floating point operations which can have information about relaxed accuracy require...
Convenience struct for specifying and reasoning about fast-math flags.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
static StringRef getMemConstraintName(ConstraintCode C)
constexpr bool isValid() const
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
static LocationSize precise(uint64_t Value)
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
TypeSize getValue() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
const MDOperand & getOperand(unsigned I) const
unsigned getNumOperands() const
Return number of MDNode operands.
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Instructions::iterator instr_iterator
Instructions::const_iterator const_instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
unsigned getNewDebugInstrNum()
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void handleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID)
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0)
Allocate and construct an extra info structure for a MachineInstr.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
bool isDebugValueList() const
void bundleWithPred()
Bundle this instruction with its predecessor.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
const MachineBasicBlock * getParent() const
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
QueryType
API for querying MachineInstr properties.
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
bool isCall(QueryType Type=AnyInBundle) const
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
unsigned getNumOperands() const
Retuns the total number of operands.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool isStackAligningInlineAsm() const
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
static uint32_t copyFlagsFromInstruction(const Instruction &I)
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isJumpTableDebugInfo() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
iterator_range< mop_iterator > operands()
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isNonListDebugValue() const
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isDebugValue() const
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
MachineOperand & getDebugOperand(unsigned Index)
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
uint32_t getFlags() const
Return the MI flags bitvector.
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
void unbundleFromSucc()
Break bundle below this instruction.
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void setPCSections(MachineFunction &MF, MDNode *MD)
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MDNode * getMetadata() const
void setIsDead(bool Val=true)
void setMetadata(const MDNode *MD)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
void setIsEarlyClobber(bool Val=true)
void setIsUndef(bool Val=true)
void setIsDebug(bool Val=true)
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Representation for a specific memory location.
Manage lifetime of a slot tracker for printing IR.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
LLVMContext & getContext() const
Get the global data context.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
An or instruction, which can be marked as "disjoint", indicating that the inputs don't have a 1 in th...
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Instruction that can have a nneg flag (zext/uitofp).
Special value supplied for machine level alias analysis.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void reserve(size_type N)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
MI-level Statepoint operands.
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual const TargetInstrInfo * getInstrInfo() const
This class represents a truncation of integer types.
The instances of the Type class are immutable: once they are created, they are never changed.
A Use represents the edge between a Value definition and its users.
LLVM Value Representation.
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
hash_code hash_value(const FixedPointSemantics &Val)
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Implement std::hash so that hash_code can be used in STL containers.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static unsigned getHashValue(const MachineInstr *const &MI)