LLVM  7.0.0svn
BPFAsmBackend.cpp
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1 //===-- BPFAsmBackend.cpp - BPF Assembler Backend -------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
11 #include "llvm/ADT/StringRef.h"
12 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCFixup.h"
14 #include "llvm/MC/MCObjectWriter.h"
16 #include <cassert>
17 #include <cstdint>
18 
19 using namespace llvm;
20 
21 namespace {
22 
23 class BPFAsmBackend : public MCAsmBackend {
24 public:
25  BPFAsmBackend(support::endianness Endian) : MCAsmBackend(Endian) {}
26  ~BPFAsmBackend() override = default;
27 
28  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
30  uint64_t Value, bool IsResolved,
31  const MCSubtargetInfo *STI) const override;
32 
33  std::unique_ptr<MCObjectTargetWriter>
34  createObjectTargetWriter() const override;
35 
36  // No instruction requires relaxation
37  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
38  const MCRelaxableFragment *DF,
39  const MCAsmLayout &Layout) const override {
40  return false;
41  }
42 
43  unsigned getNumFixupKinds() const override { return 1; }
44 
45  bool mayNeedRelaxation(const MCInst &Inst,
46  const MCSubtargetInfo &STI) const override {
47  return false;
48  }
49 
50  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
51  MCInst &Res) const override {}
52 
53  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
54 };
55 
56 } // end anonymous namespace
57 
58 bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
59  if ((Count % 8) != 0)
60  return false;
61 
62  for (uint64_t i = 0; i < Count; i += 8)
63  support::endian::write<uint64_t>(OS, 0x15000000, Endian);
64 
65  return true;
66 }
67 
68 void BPFAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
69  const MCValue &Target,
71  bool IsResolved,
72  const MCSubtargetInfo *STI) const {
73  if (Fixup.getKind() == FK_SecRel_4 || Fixup.getKind() == FK_SecRel_8) {
74  assert(Value == 0);
75  } else if (Fixup.getKind() == FK_Data_4) {
76  support::endian::write<uint32_t>(&Data[Fixup.getOffset()], Value, Endian);
77  } else if (Fixup.getKind() == FK_Data_8) {
78  support::endian::write<uint64_t>(&Data[Fixup.getOffset()], Value, Endian);
79  } else if (Fixup.getKind() == FK_PCRel_4) {
80  Value = (uint32_t)((Value - 8) / 8);
81  if (Endian == support::little) {
82  Data[Fixup.getOffset() + 1] = 0x10;
83  support::endian::write32le(&Data[Fixup.getOffset() + 4], Value);
84  } else {
85  Data[Fixup.getOffset() + 1] = 0x1;
86  support::endian::write32be(&Data[Fixup.getOffset() + 4], Value);
87  }
88  } else {
89  assert(Fixup.getKind() == FK_PCRel_2);
90  Value = (uint16_t)((Value - 8) / 8);
91  support::endian::write<uint16_t>(&Data[Fixup.getOffset() + 2], Value,
92  Endian);
93  }
94 }
95 
96 std::unique_ptr<MCObjectTargetWriter>
97 BPFAsmBackend::createObjectTargetWriter() const {
98  return createBPFELFObjectWriter(0);
99 }
100 
102  const MCSubtargetInfo &STI,
103  const MCRegisterInfo &MRI,
104  const MCTargetOptions &) {
105  return new BPFAsmBackend(support::little);
106 }
107 
109  const MCSubtargetInfo &STI,
110  const MCRegisterInfo &MRI,
111  const MCTargetOptions &) {
112  return new BPFAsmBackend(support::big);
113 }
void write32be(void *P, uint32_t V)
Definition: Endian.h:407
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
std::unique_ptr< MCObjectTargetWriter > createBPFELFObjectWriter(uint8_t OSABI)
This represents an "assembler immediate".
Definition: MCValue.h:40
void write32le(void *P, uint32_t V)
Definition: Endian.h:404
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:74
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
A four-byte section relative fixup.
Definition: MCFixup.h:42
A four-byte fixup.
Definition: MCFixup.h:26
MCAsmBackend * createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
unsigned const MachineRegisterInfo * MRI
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:291
uint32_t getOffset() const
Definition: MCFixup.h:125
A two-byte pc relative fixup.
Definition: MCFixup.h:29
A four-byte pc relative fixup.
Definition: MCFixup.h:30
MCAsmBackend * createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target - Wrapper for Target specific information.
A eight-byte section relative fixup.
Definition: MCFixup.h:43
Generic base class for all target subtargets.
A eight-byte fixup.
Definition: MCFixup.h:27
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
MCFixupKind getKind() const
Definition: MCFixup.h:123