LLVM  9.0.0svn
DemandedBits.cpp
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1 //===- DemandedBits.cpp - Determine demanded bits -------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass implements a demanded bits analysis. A demanded bit is one that
10 // contributes to a result; bits that are not demanded can be either zero or
11 // one without affecting control or data flow. For example in this sequence:
12 //
13 // %1 = add i32 %x, %y
14 // %2 = trunc i32 %1 to i16
15 //
16 // Only the lowest 16 bits of %1 are demanded; the rest are removed by the
17 // trunc.
18 //
19 //===----------------------------------------------------------------------===//
20 
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/SetVector.h"
24 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/IR/BasicBlock.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Dominators.h"
32 #include "llvm/IR/InstIterator.h"
33 #include "llvm/IR/InstrTypes.h"
34 #include "llvm/IR/Instruction.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/IR/Module.h"
38 #include "llvm/IR/Operator.h"
39 #include "llvm/IR/PassManager.h"
40 #include "llvm/IR/PatternMatch.h"
41 #include "llvm/IR/Type.h"
42 #include "llvm/IR/Use.h"
43 #include "llvm/Pass.h"
44 #include "llvm/Support/Casting.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/KnownBits.h"
48 #include <algorithm>
49 #include <cstdint>
50 
51 using namespace llvm;
52 using namespace llvm::PatternMatch;
53 
54 #define DEBUG_TYPE "demanded-bits"
55 
57 
59  "Demanded bits analysis", false, false)
63  "Demanded bits analysis", false, false)
64 
65 DemandedBitsWrapperPass::DemandedBitsWrapperPass() : FunctionPass(ID) {
67 }
68 
70  AU.setPreservesCFG();
73  AU.setPreservesAll();
74 }
75 
77  DB->print(OS);
78 }
79 
80 static bool isAlwaysLive(Instruction *I) {
81  return I->isTerminator() || isa<DbgInfoIntrinsic>(I) || I->isEHPad() ||
82  I->mayHaveSideEffects();
83 }
84 
85 void DemandedBits::determineLiveOperandBits(
86  const Instruction *UserI, const Value *Val, unsigned OperandNo,
87  const APInt &AOut, APInt &AB, KnownBits &Known, KnownBits &Known2,
88  bool &KnownBitsComputed) {
89  unsigned BitWidth = AB.getBitWidth();
90 
91  // We're called once per operand, but for some instructions, we need to
92  // compute known bits of both operands in order to determine the live bits of
93  // either (when both operands are instructions themselves). We don't,
94  // however, want to do this twice, so we cache the result in APInts that live
95  // in the caller. For the two-relevant-operands case, both operand values are
96  // provided here.
97  auto ComputeKnownBits =
98  [&](unsigned BitWidth, const Value *V1, const Value *V2) {
99  if (KnownBitsComputed)
100  return;
101  KnownBitsComputed = true;
102 
103  const DataLayout &DL = UserI->getModule()->getDataLayout();
104  Known = KnownBits(BitWidth);
105  computeKnownBits(V1, Known, DL, 0, &AC, UserI, &DT);
106 
107  if (V2) {
108  Known2 = KnownBits(BitWidth);
109  computeKnownBits(V2, Known2, DL, 0, &AC, UserI, &DT);
110  }
111  };
112 
113  switch (UserI->getOpcode()) {
114  default: break;
115  case Instruction::Call:
116  case Instruction::Invoke:
117  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(UserI))
118  switch (II->getIntrinsicID()) {
119  default: break;
120  case Intrinsic::bswap:
121  // The alive bits of the input are the swapped alive bits of
122  // the output.
123  AB = AOut.byteSwap();
124  break;
125  case Intrinsic::bitreverse:
126  // The alive bits of the input are the reversed alive bits of
127  // the output.
128  AB = AOut.reverseBits();
129  break;
130  case Intrinsic::ctlz:
131  if (OperandNo == 0) {
132  // We need some output bits, so we need all bits of the
133  // input to the left of, and including, the leftmost bit
134  // known to be one.
135  ComputeKnownBits(BitWidth, Val, nullptr);
136  AB = APInt::getHighBitsSet(BitWidth,
137  std::min(BitWidth, Known.countMaxLeadingZeros()+1));
138  }
139  break;
140  case Intrinsic::cttz:
141  if (OperandNo == 0) {
142  // We need some output bits, so we need all bits of the
143  // input to the right of, and including, the rightmost bit
144  // known to be one.
145  ComputeKnownBits(BitWidth, Val, nullptr);
146  AB = APInt::getLowBitsSet(BitWidth,
147  std::min(BitWidth, Known.countMaxTrailingZeros()+1));
148  }
149  break;
150  case Intrinsic::fshl:
151  case Intrinsic::fshr: {
152  const APInt *SA;
153  if (OperandNo == 2) {
154  // Shift amount is modulo the bitwidth. For powers of two we have
155  // SA % BW == SA & (BW - 1).
156  if (isPowerOf2_32(BitWidth))
157  AB = BitWidth - 1;
158  } else if (match(II->getOperand(2), m_APInt(SA))) {
159  // Normalize to funnel shift left. APInt shifts of BitWidth are well-
160  // defined, so no need to special-case zero shifts here.
161  uint64_t ShiftAmt = SA->urem(BitWidth);
162  if (II->getIntrinsicID() == Intrinsic::fshr)
163  ShiftAmt = BitWidth - ShiftAmt;
164 
165  if (OperandNo == 0)
166  AB = AOut.lshr(ShiftAmt);
167  else if (OperandNo == 1)
168  AB = AOut.shl(BitWidth - ShiftAmt);
169  }
170  break;
171  }
172  }
173  break;
174  case Instruction::Add:
175  case Instruction::Sub:
176  case Instruction::Mul:
177  // Find the highest live output bit. We don't need any more input
178  // bits than that (adds, and thus subtracts, ripple only to the
179  // left).
180  AB = APInt::getLowBitsSet(BitWidth, AOut.getActiveBits());
181  break;
182  case Instruction::Shl:
183  if (OperandNo == 0) {
184  const APInt *ShiftAmtC;
185  if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
186  uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
187  AB = AOut.lshr(ShiftAmt);
188 
189  // If the shift is nuw/nsw, then the high bits are not dead
190  // (because we've promised that they *must* be zero).
191  const ShlOperator *S = cast<ShlOperator>(UserI);
192  if (S->hasNoSignedWrap())
193  AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
194  else if (S->hasNoUnsignedWrap())
195  AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
196  }
197  }
198  break;
199  case Instruction::LShr:
200  if (OperandNo == 0) {
201  const APInt *ShiftAmtC;
202  if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
203  uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
204  AB = AOut.shl(ShiftAmt);
205 
206  // If the shift is exact, then the low bits are not dead
207  // (they must be zero).
208  if (cast<LShrOperator>(UserI)->isExact())
209  AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
210  }
211  }
212  break;
213  case Instruction::AShr:
214  if (OperandNo == 0) {
215  const APInt *ShiftAmtC;
216  if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
217  uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
218  AB = AOut.shl(ShiftAmt);
219  // Because the high input bit is replicated into the
220  // high-order bits of the result, if we need any of those
221  // bits, then we must keep the highest input bit.
222  if ((AOut & APInt::getHighBitsSet(BitWidth, ShiftAmt))
223  .getBoolValue())
224  AB.setSignBit();
225 
226  // If the shift is exact, then the low bits are not dead
227  // (they must be zero).
228  if (cast<AShrOperator>(UserI)->isExact())
229  AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
230  }
231  }
232  break;
233  case Instruction::And:
234  AB = AOut;
235 
236  // For bits that are known zero, the corresponding bits in the
237  // other operand are dead (unless they're both zero, in which
238  // case they can't both be dead, so just mark the LHS bits as
239  // dead).
240  ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
241  if (OperandNo == 0)
242  AB &= ~Known2.Zero;
243  else
244  AB &= ~(Known.Zero & ~Known2.Zero);
245  break;
246  case Instruction::Or:
247  AB = AOut;
248 
249  // For bits that are known one, the corresponding bits in the
250  // other operand are dead (unless they're both one, in which
251  // case they can't both be dead, so just mark the LHS bits as
252  // dead).
253  ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
254  if (OperandNo == 0)
255  AB &= ~Known2.One;
256  else
257  AB &= ~(Known.One & ~Known2.One);
258  break;
259  case Instruction::Xor:
260  case Instruction::PHI:
261  AB = AOut;
262  break;
263  case Instruction::Trunc:
264  AB = AOut.zext(BitWidth);
265  break;
266  case Instruction::ZExt:
267  AB = AOut.trunc(BitWidth);
268  break;
269  case Instruction::SExt:
270  AB = AOut.trunc(BitWidth);
271  // Because the high input bit is replicated into the
272  // high-order bits of the result, if we need any of those
273  // bits, then we must keep the highest input bit.
274  if ((AOut & APInt::getHighBitsSet(AOut.getBitWidth(),
275  AOut.getBitWidth() - BitWidth))
276  .getBoolValue())
277  AB.setSignBit();
278  break;
279  case Instruction::Select:
280  if (OperandNo != 0)
281  AB = AOut;
282  break;
283  case Instruction::ExtractElement:
284  if (OperandNo == 0)
285  AB = AOut;
286  break;
287  case Instruction::InsertElement:
288  case Instruction::ShuffleVector:
289  if (OperandNo == 0 || OperandNo == 1)
290  AB = AOut;
291  break;
292  }
293 }
294 
296  auto &AC = getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
297  auto &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
298  DB.emplace(F, AC, DT);
299  return false;
300 }
301 
303  DB.reset();
304 }
305 
306 void DemandedBits::performAnalysis() {
307  if (Analyzed)
308  // Analysis already completed for this function.
309  return;
310  Analyzed = true;
311 
312  Visited.clear();
313  AliveBits.clear();
314  DeadUses.clear();
315 
317 
318  // Collect the set of "root" instructions that are known live.
319  for (Instruction &I : instructions(F)) {
320  if (!isAlwaysLive(&I))
321  continue;
322 
323  LLVM_DEBUG(dbgs() << "DemandedBits: Root: " << I << "\n");
324  // For integer-valued instructions, set up an initial empty set of alive
325  // bits and add the instruction to the work list. For other instructions
326  // add their operands to the work list (for integer values operands, mark
327  // all bits as live).
328  Type *T = I.getType();
329  if (T->isIntOrIntVectorTy()) {
330  if (AliveBits.try_emplace(&I, T->getScalarSizeInBits(), 0).second)
331  Worklist.insert(&I);
332 
333  continue;
334  }
335 
336  // Non-integer-typed instructions...
337  for (Use &OI : I.operands()) {
338  if (Instruction *J = dyn_cast<Instruction>(OI)) {
339  Type *T = J->getType();
340  if (T->isIntOrIntVectorTy())
341  AliveBits[J] = APInt::getAllOnesValue(T->getScalarSizeInBits());
342  Worklist.insert(J);
343  }
344  }
345  // To save memory, we don't add I to the Visited set here. Instead, we
346  // check isAlwaysLive on every instruction when searching for dead
347  // instructions later (we need to check isAlwaysLive for the
348  // integer-typed instructions anyway).
349  }
350 
351  // Propagate liveness backwards to operands.
352  while (!Worklist.empty()) {
353  Instruction *UserI = Worklist.pop_back_val();
354 
355  LLVM_DEBUG(dbgs() << "DemandedBits: Visiting: " << *UserI);
356  APInt AOut;
357  if (UserI->getType()->isIntOrIntVectorTy()) {
358  AOut = AliveBits[UserI];
359  LLVM_DEBUG(dbgs() << " Alive Out: 0x"
360  << Twine::utohexstr(AOut.getLimitedValue()));
361  }
362  LLVM_DEBUG(dbgs() << "\n");
363 
364  if (!UserI->getType()->isIntOrIntVectorTy())
365  Visited.insert(UserI);
366 
367  KnownBits Known, Known2;
368  bool KnownBitsComputed = false;
369  // Compute the set of alive bits for each operand. These are anded into the
370  // existing set, if any, and if that changes the set of alive bits, the
371  // operand is added to the work-list.
372  for (Use &OI : UserI->operands()) {
373  // We also want to detect dead uses of arguments, but will only store
374  // demanded bits for instructions.
376  if (!I && !isa<Argument>(OI))
377  continue;
378 
379  Type *T = OI->getType();
380  if (T->isIntOrIntVectorTy()) {
381  unsigned BitWidth = T->getScalarSizeInBits();
382  APInt AB = APInt::getAllOnesValue(BitWidth);
383  if (UserI->getType()->isIntOrIntVectorTy() && !AOut &&
384  !isAlwaysLive(UserI)) {
385  // If all bits of the output are dead, then all bits of the input
386  // are also dead.
387  AB = APInt(BitWidth, 0);
388  } else {
389  // Bits of each operand that are used to compute alive bits of the
390  // output are alive, all others are dead.
391  determineLiveOperandBits(UserI, OI, OI.getOperandNo(), AOut, AB,
392  Known, Known2, KnownBitsComputed);
393 
394  // Keep track of uses which have no demanded bits.
395  if (AB.isNullValue())
396  DeadUses.insert(&OI);
397  else
398  DeadUses.erase(&OI);
399  }
400 
401  if (I) {
402  // If we've added to the set of alive bits (or the operand has not
403  // been previously visited), then re-queue the operand to be visited
404  // again.
405  APInt ABPrev(BitWidth, 0);
406  auto ABI = AliveBits.find(I);
407  if (ABI != AliveBits.end())
408  ABPrev = ABI->second;
409 
410  APInt ABNew = AB | ABPrev;
411  if (ABNew != ABPrev || ABI == AliveBits.end()) {
412  AliveBits[I] = std::move(ABNew);
413  Worklist.insert(I);
414  }
415  }
416  } else if (I && !Visited.count(I)) {
417  Worklist.insert(I);
418  }
419  }
420  }
421 }
422 
424  performAnalysis();
425 
426  auto Found = AliveBits.find(I);
427  if (Found != AliveBits.end())
428  return Found->second;
429 
430  const DataLayout &DL = I->getModule()->getDataLayout();
431  return APInt::getAllOnesValue(
432  DL.getTypeSizeInBits(I->getType()->getScalarType()));
433 }
434 
436  performAnalysis();
437 
438  return !Visited.count(I) && AliveBits.find(I) == AliveBits.end() &&
439  !isAlwaysLive(I);
440 }
441 
443  // We only track integer uses, everything else is assumed live.
444  if (!(*U)->getType()->isIntOrIntVectorTy())
445  return false;
446 
447  // Uses by always-live instructions are never dead.
448  Instruction *UserI = cast<Instruction>(U->getUser());
449  if (isAlwaysLive(UserI))
450  return false;
451 
452  performAnalysis();
453  if (DeadUses.count(U))
454  return true;
455 
456  // If no output bits are demanded, no input bits are demanded and the use
457  // is dead. These uses might not be explicitly present in the DeadUses map.
458  if (UserI->getType()->isIntOrIntVectorTy()) {
459  auto Found = AliveBits.find(UserI);
460  if (Found != AliveBits.end() && Found->second.isNullValue())
461  return true;
462  }
463 
464  return false;
465 }
466 
468  performAnalysis();
469  for (auto &KV : AliveBits) {
470  OS << "DemandedBits: 0x" << Twine::utohexstr(KV.second.getLimitedValue())
471  << " for " << *KV.first << '\n';
472  }
473 }
474 
476  return new DemandedBitsWrapperPass();
477 }
478 
479 AnalysisKey DemandedBitsAnalysis::Key;
480 
483  auto &AC = AM.getResult<AssumptionAnalysis>(F);
484  auto &DT = AM.getResult<DominatorTreeAnalysis>(F);
485  return DemandedBits(F, AC, DT);
486 }
487 
491  return PreservedAnalyses::all();
492 }
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, OptimizationRemarkEmitter *ORE=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
void initializeDemandedBitsWrapperPassPass(PassRegistry &)
void setSignBit()
Set the sign bit to 1.
Definition: APInt.h:1412
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)
Get the result of an analysis pass for a given IR unit.
Definition: PassManager.h:769
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
bool isInstructionDead(Instruction *I)
Return true if, during analysis, I could not be reached.
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:857
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:647
An immutable pass that tracks lazily created AssumptionCache objects.
bool isTerminator() const
Definition: Instruction.h:128
demanded bits
unsigned second
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:810
Analysis pass which computes a DominatorTree.
Definition: Dominators.h:230
F(f)
unsigned countMaxTrailingZeros() const
Returns the maximum number of trailing zero bits possible.
Definition: KnownBits.h:165
This defines the Use class.
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:47
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
APInt shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:992
bool runOnFunction(Function &F) override
runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass...
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
An analysis that produces DemandedBits for a function.
Definition: DemandedBits.h:106
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getActiveBits() const
Compute the number of active bits in the value.
Definition: APInt.h:1532
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
DemandedBits run(Function &F, FunctionAnalysisManager &AM)
Run the analysis pass over a function and produce demanded bits information.
bool isIntOrIntVectorTy() const
Return true if this is an integer type or a vector of integer types.
Definition: Type.h:202
APInt reverseBits() const
Definition: APInt.cpp:643
Value * getOperand(unsigned i) const
Definition: User.h:169
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return &#39;this&#39;.
Definition: Type.h:303
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:635
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:153
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
apint_match m_APInt(const APInt *&Res)
Match a ConstantInt or splatted ConstantVector, binding the specified pointer to the contained APInt...
Definition: PatternMatch.h:175
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition: APInt.cpp:1612
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
INITIALIZE_PASS_BEGIN(DemandedBitsWrapperPass, "demanded-bits", "Demanded bits analysis", false, false) INITIALIZE_PASS_END(DemandedBitsWrapperPass
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool mayHaveSideEffects() const
Return true if the instruction may have side effects.
Definition: Instruction.h:575
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
op_range operands()
Definition: User.h:237
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
demanded Demanded bits analysis
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition: PassManager.h:159
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:970
A function analysis which provides an AssumptionCache.
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:297
unsigned countMaxLeadingZeros() const
Returns the maximum number of leading zero bits possible.
Definition: KnownBits.h:175
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type...
Definition: Type.cpp:129
Module.h This file contains the declarations for the Module class.
static Twine utohexstr(const uint64_t &Val)
Definition: Twine.h:387
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:285
APInt getDemandedBits(Instruction *I)
Return the bits demanded from instruction I.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:55
Class for arbitrary precision integers.
Definition: APInt.h:69
void setPreservesAll()
Set by analyses that do not transform their input at all.
bool hasNoSignedWrap() const
Test whether this operation is known to never undergo signed overflow, aka the nsw property...
Definition: Operator.h:95
void print(raw_ostream &OS, const Module *M) const override
print - Print out the internal state of the pass.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value...
Definition: APInt.h:481
#define I(x, y, z)
Definition: MD5.cpp:58
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:72
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
APInt byteSwap() const
Definition: APInt.cpp:617
bool isUseDead(Use *U)
Return whether this use is dead by means of not having any demanded bits.
LLVM Value Representation.
Definition: Value.h:72
static bool isAlwaysLive(Instruction *I)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool isEHPad() const
Return true if the instruction is a variety of EH-block.
Definition: Instruction.h:586
inst_range instructions(Function *F)
Definition: InstIterator.h:133
A container for analyses that lazily runs them and caches their results.
Legacy analysis pass which computes a DominatorTree.
Definition: Dominators.h:259
This header defines various interfaces for pass management in LLVM.
FunctionPass * createDemandedBitsWrapperPass()
Create a demanded bits analysis pass.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:70
void releaseMemory() override
Clean up memory in between runs.
void print(raw_ostream &OS)
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
bool hasNoUnsignedWrap() const
Test whether this operation is known to never undergo unsigned overflow, aka the nuw property...
Definition: Operator.h:89