LLVM  8.0.0svn
LanaiMCCodeEmitter.cpp
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1 //===-- LanaiMCCodeEmitter.cpp - Convert Lanai code to machine code -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LanaiMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Lanai.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/Support/Casting.h"
29 #include <cassert>
30 #include <cstdint>
31 
32 #define DEBUG_TYPE "mccodeemitter"
33 
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 
36 namespace llvm {
37 
38 namespace {
39 
40 class LanaiMCCodeEmitter : public MCCodeEmitter {
41 public:
42  LanaiMCCodeEmitter(const MCInstrInfo &MCII, MCContext &C) {}
43  LanaiMCCodeEmitter(const LanaiMCCodeEmitter &) = delete;
44  void operator=(const LanaiMCCodeEmitter &) = delete;
45  ~LanaiMCCodeEmitter() override = default;
46 
47  // The functions below are called by TableGen generated functions for getting
48  // the binary encoding of instructions/opereands.
49 
50  // getBinaryCodeForInstr - TableGen'erated function for getting the
51  // binary encoding for an instruction.
52  uint64_t getBinaryCodeForInstr(const MCInst &Inst,
53  SmallVectorImpl<MCFixup> &Fixups,
54  const MCSubtargetInfo &SubtargetInfo) const;
55 
56  // getMachineOpValue - Return binary encoding of operand. If the machine
57  // operand requires relocation, record the relocation and return zero.
58  unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
59  SmallVectorImpl<MCFixup> &Fixups,
60  const MCSubtargetInfo &SubtargetInfo) const;
61 
62  unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
63  SmallVectorImpl<MCFixup> &Fixups,
64  const MCSubtargetInfo &SubtargetInfo) const;
65 
66  unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
67  SmallVectorImpl<MCFixup> &Fixups,
68  const MCSubtargetInfo &SubtargetInfo) const;
69 
70  unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
71  SmallVectorImpl<MCFixup> &Fixups,
72  const MCSubtargetInfo &SubtargetInfo) const;
73 
74  unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
75  SmallVectorImpl<MCFixup> &Fixups,
76  const MCSubtargetInfo &SubtargetInfo) const;
77 
78  void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream,
79  SmallVectorImpl<MCFixup> &Fixups,
80  const MCSubtargetInfo &SubtargetInfo) const override;
81 
82  unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
83  const MCSubtargetInfo &STI) const;
84 
85  unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
86  const MCSubtargetInfo &STI) const;
87 };
88 
89 } // end anonymous namespace
90 
91 static Lanai::Fixups FixupKind(const MCExpr *Expr) {
92  if (isa<MCSymbolRefExpr>(Expr))
93  return Lanai::FIXUP_LANAI_21;
94  if (const LanaiMCExpr *McExpr = dyn_cast<LanaiMCExpr>(Expr)) {
95  LanaiMCExpr::VariantKind ExprKind = McExpr->getKind();
96  switch (ExprKind) {
98  return Lanai::FIXUP_LANAI_21;
103  }
104  }
105  return Lanai::Fixups(0);
106 }
107 
108 // getMachineOpValue - Return binary encoding of operand. If the machine
109 // operand requires relocation, record the relocation and return zero.
110 unsigned LanaiMCCodeEmitter::getMachineOpValue(
111  const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups,
112  const MCSubtargetInfo &SubtargetInfo) const {
113  if (MCOp.isReg())
114  return getLanaiRegisterNumbering(MCOp.getReg());
115  if (MCOp.isImm())
116  return static_cast<unsigned>(MCOp.getImm());
117 
118  // MCOp must be an expression
119  assert(MCOp.isExpr());
120  const MCExpr *Expr = MCOp.getExpr();
121 
122  // Extract the symbolic reference side of a binary expression.
123  if (Expr->getKind() == MCExpr::Binary) {
124  const MCBinaryExpr *BinaryExpr = static_cast<const MCBinaryExpr *>(Expr);
125  Expr = BinaryExpr->getLHS();
126  }
127 
128  assert(isa<LanaiMCExpr>(Expr) || Expr->getKind() == MCExpr::SymbolRef);
129  // Push fixup (all info is contained within)
130  Fixups.push_back(
131  MCFixup::create(0, MCOp.getExpr(), MCFixupKind(FixupKind(Expr))));
132  return 0;
133 }
134 
135 // Helper function to adjust P and Q bits on load and store instructions.
136 static unsigned adjustPqBits(const MCInst &Inst, unsigned Value,
137  unsigned PBitShift, unsigned QBitShift) {
138  const MCOperand AluOp = Inst.getOperand(3);
139  unsigned AluCode = AluOp.getImm();
140 
141  // Set the P bit to one iff the immediate is nonzero and not a post-op
142  // instruction.
143  const MCOperand Op2 = Inst.getOperand(2);
144  Value &= ~(1 << PBitShift);
145  if (!LPAC::isPostOp(AluCode) &&
146  ((Op2.isImm() && Op2.getImm() != 0) ||
147  (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
148  Value |= (1 << PBitShift);
149 
150  // Set the Q bit to one iff it is a post- or pre-op instruction.
151  assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
152  "Expected register operand.");
153  Value &= ~(1 << QBitShift);
154  if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
155  (Op2.isReg() && Op2.getReg() != Lanai::R0)))
156  Value |= (1 << QBitShift);
157 
158  return Value;
159 }
160 
161 unsigned
162 LanaiMCCodeEmitter::adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
163  const MCSubtargetInfo &STI) const {
164  return adjustPqBits(Inst, Value, 17, 16);
165 }
166 
167 unsigned
168 LanaiMCCodeEmitter::adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
169  const MCSubtargetInfo &STI) const {
170  return adjustPqBits(Inst, Value, 11, 10);
171 }
172 
173 void LanaiMCCodeEmitter::encodeInstruction(
174  const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &Fixups,
175  const MCSubtargetInfo &SubtargetInfo) const {
176  // Get instruction encoding and emit it
177  unsigned Value = getBinaryCodeForInstr(Inst, Fixups, SubtargetInfo);
178  ++MCNumEmitted; // Keep track of the number of emitted insns.
179 
180  // Emit bytes in big-endian
181  for (int i = (4 - 1) * 8; i >= 0; i -= 8)
182  Ostream << static_cast<char>((Value >> i) & 0xff);
183 }
184 
185 // Encode Lanai Memory Operand
186 unsigned LanaiMCCodeEmitter::getRiMemoryOpValue(
187  const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
188  const MCSubtargetInfo &SubtargetInfo) const {
189  unsigned Encoding;
190  const MCOperand Op1 = Inst.getOperand(OpNo + 0);
191  const MCOperand Op2 = Inst.getOperand(OpNo + 1);
192  const MCOperand AluOp = Inst.getOperand(OpNo + 2);
193 
194  assert(Op1.isReg() && "First operand is not register.");
195  assert((Op2.isImm() || Op2.isExpr()) &&
196  "Second operand is neither an immediate nor an expression.");
197  assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
198  "Register immediate only supports addition operator");
199 
200  Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18);
201  if (Op2.isImm()) {
202  assert(isInt<16>(Op2.getImm()) &&
203  "Constant value truncated (limited to 16-bit)");
204 
205  Encoding |= (Op2.getImm() & 0xffff);
206  if (Op2.getImm() != 0) {
207  if (LPAC::isPreOp(AluOp.getImm()))
208  Encoding |= (0x3 << 16);
209  if (LPAC::isPostOp(AluOp.getImm()))
210  Encoding |= (0x1 << 16);
211  }
212  } else
213  getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
214 
215  return Encoding;
216 }
217 
218 unsigned LanaiMCCodeEmitter::getRrMemoryOpValue(
219  const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
220  const MCSubtargetInfo &SubtargetInfo) const {
221  unsigned Encoding;
222  const MCOperand Op1 = Inst.getOperand(OpNo + 0);
223  const MCOperand Op2 = Inst.getOperand(OpNo + 1);
224  const MCOperand AluMCOp = Inst.getOperand(OpNo + 2);
225 
226  assert(Op1.isReg() && "First operand is not register.");
227  Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15);
228  assert(Op2.isReg() && "Second operand is not register.");
229  Encoding |= (getLanaiRegisterNumbering(Op2.getReg()) << 10);
230 
231  assert(AluMCOp.isImm() && "Third operator is not immediate.");
232  // Set BBB
233  unsigned AluOp = AluMCOp.getImm();
234  Encoding |= LPAC::encodeLanaiAluCode(AluOp) << 5;
235  // Set P and Q
236  if (LPAC::isPreOp(AluOp))
237  Encoding |= (0x3 << 8);
238  if (LPAC::isPostOp(AluOp))
239  Encoding |= (0x1 << 8);
240  // Set JJJJ
241  switch (LPAC::getAluOp(AluOp)) {
242  case LPAC::SHL:
243  case LPAC::SRL:
244  Encoding |= 0x10;
245  break;
246  case LPAC::SRA:
247  Encoding |= 0x18;
248  break;
249  default:
250  break;
251  }
252 
253  return Encoding;
254 }
255 
256 unsigned
257 LanaiMCCodeEmitter::getSplsOpValue(const MCInst &Inst, unsigned OpNo,
258  SmallVectorImpl<MCFixup> &Fixups,
259  const MCSubtargetInfo &SubtargetInfo) const {
260  unsigned Encoding;
261  const MCOperand Op1 = Inst.getOperand(OpNo + 0);
262  const MCOperand Op2 = Inst.getOperand(OpNo + 1);
263  const MCOperand AluOp = Inst.getOperand(OpNo + 2);
264 
265  assert(Op1.isReg() && "First operand is not register.");
266  assert((Op2.isImm() || Op2.isExpr()) &&
267  "Second operand is neither an immediate nor an expression.");
268  assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
269  "Register immediate only supports addition operator");
270 
271  Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12);
272  if (Op2.isImm()) {
273  assert(isInt<10>(Op2.getImm()) &&
274  "Constant value truncated (limited to 10-bit)");
275 
276  Encoding |= (Op2.getImm() & 0x3ff);
277  if (Op2.getImm() != 0) {
278  if (LPAC::isPreOp(AluOp.getImm()))
279  Encoding |= (0x3 << 10);
280  if (LPAC::isPostOp(AluOp.getImm()))
281  Encoding |= (0x1 << 10);
282  }
283  } else
284  getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
285 
286  return Encoding;
287 }
288 
290  const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
291  const MCSubtargetInfo &SubtargetInfo) const {
292  const MCOperand &MCOp = Inst.getOperand(OpNo);
293  if (MCOp.isReg() || MCOp.isImm())
294  return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
295 
296  Fixups.push_back(MCFixup::create(
297  0, MCOp.getExpr(), static_cast<MCFixupKind>(Lanai::FIXUP_LANAI_25)));
298 
299  return 0;
300 }
301 
302 #include "LanaiGenMCCodeEmitter.inc"
303 
304 } // end namespace llvm
305 
308  const MCRegisterInfo & /*MRI*/,
309  MCContext &context) {
310  return new LanaiMCCodeEmitter(InstrInfo, context);
311 }
uint64_t CallInst * C
bool isImm() const
Definition: MCInst.h:59
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static bool modifiesOp(unsigned AluOp)
Definition: LanaiAluCode.h:73
static unsigned getAluOp(unsigned AluOp)
Definition: LanaiAluCode.h:54
bool isReg() const
Definition: MCInst.h:58
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:563
MCCodeEmitter * createLanaiMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
static unsigned getLanaiRegisterNumbering(unsigned Reg)
Definition: LanaiBaseInfo.h:41
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
static Lanai::Fixups FixupKind(const MCExpr *Expr)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
const MCExpr * getExpr() const
Definition: MCInst.h:96
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static bool isPreOp(unsigned AluOp)
Definition: LanaiAluCode.h:59
int64_t getImm() const
Definition: MCInst.h:76
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
bool isExpr() const
Definition: MCInst.h:61
Binary assembler expressions.
Definition: MCExpr.h:416
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:90
STATISTIC(MCNumEmitted, "Number of MC instructions emitted")
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
static bool isPostOp(unsigned AluOp)
Definition: LanaiAluCode.h:61
Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:41
static unsigned encodeLanaiAluCode(unsigned AluOp)
Definition: LanaiAluCode.h:49
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
Binary expressions.
Definition: MCExpr.h:39
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
static unsigned adjustPqBits(const MCInst &Inst, unsigned Value, unsigned PBitShift, unsigned QBitShift)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35