LLVM  6.0.0svn
Macros | Functions
ARMMCCodeEmitter.cpp File Reference
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "MCTargetDesc/ARMFixupKinds.h"
#include "MCTargetDesc/ARMMCExpr.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstdlib>
#include "ARMGenMCCodeEmitter.inc"
Include dependency graph for ARMMCCodeEmitter.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "mccodeemitter"
 

Functions

 STATISTIC (MCNumEmitted, "Number of MC instructions emitted.")
 
 STATISTIC (MCNumCPRelocations, "Number of constant pool relocations created.")
 
static uint32_t getBranchTargetOpValue (const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
 getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immediate or requires a fixup. More...
 
static int32_t encodeThumbBLOffset (int32_t offset)
 
static bool HasConditionalBranch (const MCInst &MI)
 Return true if this branch has a non-always predication. More...
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "mccodeemitter"

Definition at line 44 of file ARMMCCodeEmitter.cpp.

Function Documentation

◆ encodeThumbBLOffset()

static int32_t encodeThumbBLOffset ( int32_t  offset)
static

◆ getBranchTargetOpValue()

static uint32_t getBranchTargetOpValue ( const MCInst MI,
unsigned  OpIdx,
unsigned  FixupKind,
SmallVectorImpl< MCFixup > &  Fixups,
const MCSubtargetInfo STI 
)
static

◆ HasConditionalBranch()

static bool HasConditionalBranch ( const MCInst MI)
static

Return true if this branch has a non-always predication.

Definition at line 688 of file ARMMCCodeEmitter.cpp.

References llvm::abs(), llvm::ARM_AM::add, llvm::ARMCC::AL, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::ARM_AM::asr, assert(), llvm::MCInst::begin(), llvm::countLeadingZeros(), llvm::countTrailingZeros(), llvm::MCFixup::create(), E, llvm::MCInst::end(), false, llvm::ARM::fixup_arm_adr_pcrel_12, llvm::ARM::fixup_arm_blx, llvm::ARM::fixup_arm_condbl, llvm::ARM::fixup_arm_condbranch, llvm::ARM::fixup_arm_ldst_pcrel_12, llvm::ARM::fixup_arm_movt_hi16, llvm::ARM::fixup_arm_movw_lo16, llvm::ARM::fixup_arm_pcrel_10, llvm::ARM::fixup_arm_pcrel_10_unscaled, llvm::ARM::fixup_arm_pcrel_9, llvm::ARM::fixup_arm_thumb_cp, llvm::ARM::fixup_arm_uncondbl, llvm::ARM::fixup_arm_uncondbranch, llvm::ARM::fixup_t2_adr_pcrel_12, llvm::ARM::fixup_t2_condbranch, llvm::ARM::fixup_t2_ldst_pcrel_12, llvm::ARM::fixup_t2_movt_hi16, llvm::ARM::fixup_t2_movw_lo16, llvm::ARM::fixup_t2_pcrel_10, llvm::ARM::fixup_t2_pcrel_9, llvm::ARM::fixup_t2_uncondbranch, llvm::ARM::fixup_thumb_adr_pcrel_10, llvm::ARMII::FormMask, llvm::MCInstrInfo::get(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::ARM_AM::getAM5Offset(), llvm::ARM_AM::getAM5Op(), getBranchTargetOpValue(), llvm::MCRegisterInfo::getEncodingValue(), llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::ARMMCExpr::getKind(), llvm::MCExpr::getKind(), llvm::MCInst::getLoc(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), llvm::MCContext::getRegisterInfo(), llvm::MCInstrDesc::getSize(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARMMCExpr::getSubExpr(), I, llvm::X86II::Imm8, llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), isReg(), llvm::MCOperand::isReg(), isThumb(), Kind, LLVM_FALLTHROUGH, llvm_unreachable, llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, MRI, llvm::ARMII::Pseudo, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ARMII::RegRsShift, llvm::report_fatal_error(), llvm::ARM_AM::ror, llvm::ARM_AM::rrx, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size, llvm::MCExpr::Target, llvm::MCInstrDesc::TSFlags, llvm::ARMMCExpr::VK_ARM_HI16, and llvm::ARMMCExpr::VK_ARM_LO16.

◆ STATISTIC() [1/2]

STATISTIC ( MCNumEmitted  ,
"Number of MC instructions emitted."   
)

◆ STATISTIC() [2/2]

STATISTIC ( MCNumCPRelocations  ,
"Number of constant pool relocations created."   
)