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ARMMCCodeEmitter.cpp
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1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARMMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <cstdlib>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "mccodeemitter"
44 
45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
47 
48 namespace {
49 
50 class ARMMCCodeEmitter : public MCCodeEmitter {
51  const MCInstrInfo &MCII;
52  const MCContext &CTX;
53  bool IsLittleEndian;
54 
55 public:
56  ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
57  : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58  }
59  ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
60  ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
61  ~ARMMCCodeEmitter() override = default;
62 
63  bool isThumb(const MCSubtargetInfo &STI) const {
64  return STI.getFeatureBits()[ARM::ModeThumb];
65  }
66 
67  bool isThumb2(const MCSubtargetInfo &STI) const {
68  return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
69  }
70 
71  bool isTargetMachO(const MCSubtargetInfo &STI) const {
72  const Triple &TT = STI.getTargetTriple();
73  return TT.isOSBinFormatMachO();
74  }
75 
76  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77 
78  // getBinaryCodeForInstr - TableGen'erated function for getting the
79  // binary encoding for an instruction.
80  uint64_t getBinaryCodeForInstr(const MCInst &MI,
82  const MCSubtargetInfo &STI) const;
83 
84  /// getMachineOpValue - Return binary encoding of operand. If the machine
85  /// operand requires relocation, record the relocation and return zero.
86  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
88  const MCSubtargetInfo &STI) const;
89 
90  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
91  /// the specified operand. This is used for operands with :lower16: and
92  /// :upper16: prefixes.
93  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
95  const MCSubtargetInfo &STI) const;
96 
97  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98  unsigned &Reg, unsigned &Imm,
100  const MCSubtargetInfo &STI) const;
101 
102  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103  /// BL branch target.
104  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
106  const MCSubtargetInfo &STI) const;
107 
108  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109  /// BLX branch target.
110  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
112  const MCSubtargetInfo &STI) const;
113 
114  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
117  const MCSubtargetInfo &STI) const;
118 
119  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
122  const MCSubtargetInfo &STI) const;
123 
124  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
125  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
127  const MCSubtargetInfo &STI) const;
128 
129  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130  /// branch target.
131  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
133  const MCSubtargetInfo &STI) const;
134 
135  /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136  /// immediate Thumb2 direct branch target.
137  uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
139  const MCSubtargetInfo &STI) const;
140 
141  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142  /// branch target.
143  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
145  const MCSubtargetInfo &STI) const;
146  uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
148  const MCSubtargetInfo &STI) const;
149  uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
151  const MCSubtargetInfo &STI) const;
152 
153  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154  /// ADR label target.
155  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
157  const MCSubtargetInfo &STI) const;
158  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
160  const MCSubtargetInfo &STI) const;
161  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
163  const MCSubtargetInfo &STI) const;
164 
165 
166  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
167  /// operand.
168  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
170  const MCSubtargetInfo &STI) const;
171 
172  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
173  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
175  const MCSubtargetInfo &STI) const;
176 
177  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
178  /// operand.
179  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
181  const MCSubtargetInfo &STI) const;
182 
183  /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
184  /// operand.
185  uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
187  const MCSubtargetInfo &STI) const;
188 
189  /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
190  /// operand.
191  uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
193  const MCSubtargetInfo &STI) const;
194 
195 
196  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
197  /// operand as needed by load/store instructions.
198  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
200  const MCSubtargetInfo &STI) const;
201 
202  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
203  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
205  const MCSubtargetInfo &STI) const {
207  switch (Mode) {
208  default: llvm_unreachable("Unknown addressing sub-mode!");
209  case ARM_AM::da: return 0;
210  case ARM_AM::ia: return 1;
211  case ARM_AM::db: return 2;
212  case ARM_AM::ib: return 3;
213  }
214  }
215 
216  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
217  ///
218  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
219  switch (ShOpc) {
220  case ARM_AM::no_shift:
221  case ARM_AM::lsl: return 0;
222  case ARM_AM::lsr: return 1;
223  case ARM_AM::asr: return 2;
224  case ARM_AM::ror:
225  case ARM_AM::rrx: return 3;
226  }
227  llvm_unreachable("Invalid ShiftOpc!");
228  }
229 
230  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
231  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
232  SmallVectorImpl<MCFixup> &Fixups,
233  const MCSubtargetInfo &STI) const;
234 
235  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
236  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
237  SmallVectorImpl<MCFixup> &Fixups,
238  const MCSubtargetInfo &STI) const;
239 
240  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
241  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
242  SmallVectorImpl<MCFixup> &Fixups,
243  const MCSubtargetInfo &STI) const;
244 
245  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
246  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
247  SmallVectorImpl<MCFixup> &Fixups,
248  const MCSubtargetInfo &STI) const;
249 
250  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
251  /// operand.
252  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
253  SmallVectorImpl<MCFixup> &Fixups,
254  const MCSubtargetInfo &STI) const;
255 
256  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
257  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
258  SmallVectorImpl<MCFixup> &Fixups,
259  const MCSubtargetInfo &STI) const;
260 
261  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
262  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
263  SmallVectorImpl<MCFixup> &Fixups,
264  const MCSubtargetInfo &STI) const;
265 
266  /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
267  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
268  SmallVectorImpl<MCFixup> &Fixups,
269  const MCSubtargetInfo &STI) const;
270 
271  /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
272  uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
273  SmallVectorImpl<MCFixup> &Fixups,
274  const MCSubtargetInfo &STI) const;
275 
276  /// getCCOutOpValue - Return encoding of the 's' bit.
277  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
278  SmallVectorImpl<MCFixup> &Fixups,
279  const MCSubtargetInfo &STI) const {
280  // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
281  // '1' respectively.
282  return MI.getOperand(Op).getReg() == ARM::CPSR;
283  }
284 
285  /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
286  unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
287  SmallVectorImpl<MCFixup> &Fixups,
288  const MCSubtargetInfo &STI) const {
289  const MCOperand &MO = MI.getOperand(Op);
290 
291  // We expect MO to be an immediate or an expression,
292  // if it is an immediate - that's fine, just encode the value.
293  // Otherwise - create a Fixup.
294  if (MO.isExpr()) {
295  const MCExpr *Expr = MO.getExpr();
296  // In instruction code this value always encoded as lowest 12 bits,
297  // so we don't have to perform any specific adjustments.
298  // Due to requirements of relocatable records we have to use FK_Data_4.
299  // See ARMELFObjectWriter::ExplicitRelSym and
300  // ARMELFObjectWriter::GetRelocTypeInner for more details.
302  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
303  return 0;
304  }
305 
306  unsigned SoImm = MO.getImm();
307  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
308  assert(SoImmVal != -1 && "Not a valid so_imm value!");
309 
310  // Encode rotate_imm.
311  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
313 
314  // Encode immed_8.
315  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
316  return Binary;
317  }
318 
319  unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
320  SmallVectorImpl<MCFixup> &Fixups,
321  const MCSubtargetInfo &ST) const {
322  const MCOperand &MO = MI.getOperand(Op);
323 
324  // Support for fixups (MCFixup)
325  if (MO.isExpr()) {
326  const MCExpr *Expr = MO.getExpr();
327  // Fixups resolve to plain values that need to be encoded.
329  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
330  return 0;
331  }
332 
333  // Immediate is already in its encoded format
334  return MO.getImm();
335  }
336 
337  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
338  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
339  SmallVectorImpl<MCFixup> &Fixups,
340  const MCSubtargetInfo &STI) const {
341  const MCOperand &MO = MI.getOperand(Op);
342 
343  // Support for fixups (MCFixup)
344  if (MO.isExpr()) {
345  const MCExpr *Expr = MO.getExpr();
346  // Fixups resolve to plain values that need to be encoded.
348  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
349  return 0;
350  }
351  unsigned SoImm = MO.getImm();
352  unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
353  assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
354  return Encoded;
355  }
356 
357  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
358  SmallVectorImpl<MCFixup> &Fixups,
359  const MCSubtargetInfo &STI) const;
360  unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
361  SmallVectorImpl<MCFixup> &Fixups,
362  const MCSubtargetInfo &STI) const;
363  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
364  SmallVectorImpl<MCFixup> &Fixups,
365  const MCSubtargetInfo &STI) const;
366 
367  /// getSORegOpValue - Return an encoded so_reg shifted register value.
368  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
369  SmallVectorImpl<MCFixup> &Fixups,
370  const MCSubtargetInfo &STI) const;
371  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
372  SmallVectorImpl<MCFixup> &Fixups,
373  const MCSubtargetInfo &STI) const;
374  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
375  SmallVectorImpl<MCFixup> &Fixups,
376  const MCSubtargetInfo &STI) const;
377 
378  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
379  SmallVectorImpl<MCFixup> &Fixups,
380  const MCSubtargetInfo &STI) const {
381  return 64 - MI.getOperand(Op).getImm();
382  }
383 
384  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
385  SmallVectorImpl<MCFixup> &Fixups,
386  const MCSubtargetInfo &STI) const;
387 
388  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
389  SmallVectorImpl<MCFixup> &Fixups,
390  const MCSubtargetInfo &STI) const;
391  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
392  SmallVectorImpl<MCFixup> &Fixups,
393  const MCSubtargetInfo &STI) const;
394  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
395  SmallVectorImpl<MCFixup> &Fixups,
396  const MCSubtargetInfo &STI) const;
397  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
398  SmallVectorImpl<MCFixup> &Fixups,
399  const MCSubtargetInfo &STI) const;
400  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
401  SmallVectorImpl<MCFixup> &Fixups,
402  const MCSubtargetInfo &STI) const;
403 
404  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
405  SmallVectorImpl<MCFixup> &Fixups,
406  const MCSubtargetInfo &STI) const;
407  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
408  SmallVectorImpl<MCFixup> &Fixups,
409  const MCSubtargetInfo &STI) const;
410  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
411  SmallVectorImpl<MCFixup> &Fixups,
412  const MCSubtargetInfo &STI) const;
413  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
414  SmallVectorImpl<MCFixup> &Fixups,
415  const MCSubtargetInfo &STI) const;
416 
417  unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
418  SmallVectorImpl<MCFixup> &Fixups,
419  const MCSubtargetInfo &STI) const;
420 
421  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
422  unsigned EncodedValue,
423  const MCSubtargetInfo &STI) const;
424  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
425  unsigned EncodedValue,
426  const MCSubtargetInfo &STI) const;
427  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
428  unsigned EncodedValue,
429  const MCSubtargetInfo &STI) const;
430  unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
431  unsigned EncodedValue,
432  const MCSubtargetInfo &STI) const;
433 
434  unsigned VFPThumb2PostEncoder(const MCInst &MI,
435  unsigned EncodedValue,
436  const MCSubtargetInfo &STI) const;
437 
438  void EmitByte(unsigned char C, raw_ostream &OS) const {
439  OS << (char)C;
440  }
441 
442  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
443  // Output the constant in little endian byte order.
444  for (unsigned i = 0; i != Size; ++i) {
445  unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
446  EmitByte((Val >> Shift) & 0xff, OS);
447  }
448  }
449 
450  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
451  SmallVectorImpl<MCFixup> &Fixups,
452  const MCSubtargetInfo &STI) const override;
453 };
454 
455 } // end anonymous namespace
456 
457 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
458 /// instructions, and rewrite them to their Thumb2 form if we are currently in
459 /// Thumb2 mode.
460 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
461  unsigned EncodedValue,
462  const MCSubtargetInfo &STI) const {
463  if (isThumb2(STI)) {
464  // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
465  // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
466  // set to 1111.
467  unsigned Bit24 = EncodedValue & 0x01000000;
468  unsigned Bit28 = Bit24 << 4;
469  EncodedValue &= 0xEFFFFFFF;
470  EncodedValue |= Bit28;
471  EncodedValue |= 0x0F000000;
472  }
473 
474  return EncodedValue;
475 }
476 
477 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
478 /// instructions, and rewrite them to their Thumb2 form if we are currently in
479 /// Thumb2 mode.
480 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
481  unsigned EncodedValue,
482  const MCSubtargetInfo &STI) const {
483  if (isThumb2(STI)) {
484  EncodedValue &= 0xF0FFFFFF;
485  EncodedValue |= 0x09000000;
486  }
487 
488  return EncodedValue;
489 }
490 
491 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
492 /// instructions, and rewrite them to their Thumb2 form if we are currently in
493 /// Thumb2 mode.
494 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
495  unsigned EncodedValue,
496  const MCSubtargetInfo &STI) const {
497  if (isThumb2(STI)) {
498  EncodedValue &= 0x00FFFFFF;
499  EncodedValue |= 0xEE000000;
500  }
501 
502  return EncodedValue;
503 }
504 
505 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
506 /// if we are in Thumb2.
507 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
508  unsigned EncodedValue,
509  const MCSubtargetInfo &STI) const {
510  if (isThumb2(STI)) {
511  EncodedValue |= 0xC000000; // Set bits 27-26
512  }
513 
514  return EncodedValue;
515 }
516 
517 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
518 /// them to their Thumb2 form if we are currently in Thumb2 mode.
519 unsigned ARMMCCodeEmitter::
520 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
521  const MCSubtargetInfo &STI) const {
522  if (isThumb2(STI)) {
523  EncodedValue &= 0x0FFFFFFF;
524  EncodedValue |= 0xE0000000;
525  }
526  return EncodedValue;
527 }
528 
529 /// getMachineOpValue - Return binary encoding of operand. If the machine
530 /// operand requires relocation, record the relocation and return zero.
531 unsigned ARMMCCodeEmitter::
532 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
533  SmallVectorImpl<MCFixup> &Fixups,
534  const MCSubtargetInfo &STI) const {
535  if (MO.isReg()) {
536  unsigned Reg = MO.getReg();
537  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
538 
539  // Q registers are encoded as 2x their register number.
540  switch (Reg) {
541  default:
542  return RegNo;
543  case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
544  case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
545  case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
546  case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
547  return 2 * RegNo;
548  }
549  } else if (MO.isImm()) {
550  return static_cast<unsigned>(MO.getImm());
551  } else if (MO.isFPImm()) {
552  return static_cast<unsigned>(APFloat(MO.getFPImm())
553  .bitcastToAPInt().getHiBits(32).getLimitedValue());
554  }
555 
556  llvm_unreachable("Unable to encode MCOperand!");
557 }
558 
559 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
560 bool ARMMCCodeEmitter::
561 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
562  unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
563  const MCSubtargetInfo &STI) const {
564  const MCOperand &MO = MI.getOperand(OpIdx);
565  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
566 
567  Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
568 
569  int32_t SImm = MO1.getImm();
570  bool isAdd = true;
571 
572  // Special value for #-0
573  if (SImm == INT32_MIN) {
574  SImm = 0;
575  isAdd = false;
576  }
577 
578  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
579  if (SImm < 0) {
580  SImm = -SImm;
581  isAdd = false;
582  }
583 
584  Imm = SImm;
585  return isAdd;
586 }
587 
588 /// getBranchTargetOpValue - Helper function to get the branch target operand,
589 /// which is either an immediate or requires a fixup.
590 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
591  unsigned FixupKind,
592  SmallVectorImpl<MCFixup> &Fixups,
593  const MCSubtargetInfo &STI) {
594  const MCOperand &MO = MI.getOperand(OpIdx);
595 
596  // If the destination is an immediate, we have nothing to do.
597  if (MO.isImm()) return MO.getImm();
598  assert(MO.isExpr() && "Unexpected branch target type!");
599  const MCExpr *Expr = MO.getExpr();
600  MCFixupKind Kind = MCFixupKind(FixupKind);
601  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
602 
603  // All of the information is in the fixup.
604  return 0;
605 }
606 
607 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
608 // determined by negating them and XOR'ing them with bit 23.
609 static int32_t encodeThumbBLOffset(int32_t offset) {
610  offset >>= 1;
611  uint32_t S = (offset & 0x800000) >> 23;
612  uint32_t J1 = (offset & 0x400000) >> 22;
613  uint32_t J2 = (offset & 0x200000) >> 21;
614  J1 = (~J1 & 0x1);
615  J2 = (~J2 & 0x1);
616  J1 ^= S;
617  J2 ^= S;
618 
619  offset &= ~0x600000;
620  offset |= J1 << 22;
621  offset |= J2 << 21;
622 
623  return offset;
624 }
625 
626 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
627 uint32_t ARMMCCodeEmitter::
628 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
629  SmallVectorImpl<MCFixup> &Fixups,
630  const MCSubtargetInfo &STI) const {
631  const MCOperand MO = MI.getOperand(OpIdx);
632  if (MO.isExpr())
634  Fixups, STI);
635  return encodeThumbBLOffset(MO.getImm());
636 }
637 
638 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
639 /// BLX branch target.
640 uint32_t ARMMCCodeEmitter::
641 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
642  SmallVectorImpl<MCFixup> &Fixups,
643  const MCSubtargetInfo &STI) const {
644  const MCOperand MO = MI.getOperand(OpIdx);
645  if (MO.isExpr())
647  Fixups, STI);
648  return encodeThumbBLOffset(MO.getImm());
649 }
650 
651 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
652 uint32_t ARMMCCodeEmitter::
653 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
654  SmallVectorImpl<MCFixup> &Fixups,
655  const MCSubtargetInfo &STI) const {
656  const MCOperand MO = MI.getOperand(OpIdx);
657  if (MO.isExpr())
659  Fixups, STI);
660  return (MO.getImm() >> 1);
661 }
662 
663 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
664 uint32_t ARMMCCodeEmitter::
665 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
666  SmallVectorImpl<MCFixup> &Fixups,
667  const MCSubtargetInfo &STI) const {
668  const MCOperand MO = MI.getOperand(OpIdx);
669  if (MO.isExpr())
671  Fixups, STI);
672  return (MO.getImm() >> 1);
673 }
674 
675 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
676 uint32_t ARMMCCodeEmitter::
677 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
678  SmallVectorImpl<MCFixup> &Fixups,
679  const MCSubtargetInfo &STI) const {
680  const MCOperand MO = MI.getOperand(OpIdx);
681  if (MO.isExpr())
683  return (MO.getImm() >> 1);
684 }
685 
686 /// Return true if this branch has a non-always predication
687 static bool HasConditionalBranch(const MCInst &MI) {
688  int NumOp = MI.getNumOperands();
689  if (NumOp >= 2) {
690  for (int i = 0; i < NumOp-1; ++i) {
691  const MCOperand &MCOp1 = MI.getOperand(i);
692  const MCOperand &MCOp2 = MI.getOperand(i + 1);
693  if (MCOp1.isImm() && MCOp2.isReg() &&
694  (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
695  if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
696  return true;
697  }
698  }
699  }
700  return false;
701 }
702 
703 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
704 /// target.
706 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
707  SmallVectorImpl<MCFixup> &Fixups,
708  const MCSubtargetInfo &STI) const {
709  // FIXME: This really, really shouldn't use TargetMachine. We don't want
710  // coupling between MC and TM anywhere we can help it.
711  if (isThumb2(STI))
712  return
713  ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
714  return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
715 }
716 
717 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
718 /// target.
719 uint32_t ARMMCCodeEmitter::
720 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
721  SmallVectorImpl<MCFixup> &Fixups,
722  const MCSubtargetInfo &STI) const {
723  const MCOperand MO = MI.getOperand(OpIdx);
724  if (MO.isExpr()) {
725  if (HasConditionalBranch(MI))
727  ARM::fixup_arm_condbranch, Fixups, STI);
729  ARM::fixup_arm_uncondbranch, Fixups, STI);
730  }
731 
732  return MO.getImm() >> 2;
733 }
734 
735 uint32_t ARMMCCodeEmitter::
736 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
737  SmallVectorImpl<MCFixup> &Fixups,
738  const MCSubtargetInfo &STI) const {
739  const MCOperand MO = MI.getOperand(OpIdx);
740  if (MO.isExpr()) {
741  if (HasConditionalBranch(MI))
743  ARM::fixup_arm_condbl, Fixups, STI);
745  }
746 
747  return MO.getImm() >> 2;
748 }
749 
750 uint32_t ARMMCCodeEmitter::
751 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
752  SmallVectorImpl<MCFixup> &Fixups,
753  const MCSubtargetInfo &STI) const {
754  const MCOperand MO = MI.getOperand(OpIdx);
755  if (MO.isExpr())
756  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
757 
758  return MO.getImm() >> 1;
759 }
760 
761 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
762 /// immediate branch target.
763 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
764  const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
765  const MCSubtargetInfo &STI) const {
766  unsigned Val = 0;
767  const MCOperand MO = MI.getOperand(OpIdx);
768 
769  if(MO.isExpr())
771  else
772  Val = MO.getImm() >> 1;
773 
774  bool I = (Val & 0x800000);
775  bool J1 = (Val & 0x400000);
776  bool J2 = (Val & 0x200000);
777  if (I ^ J1)
778  Val &= ~0x400000;
779  else
780  Val |= 0x400000;
781 
782  if (I ^ J2)
783  Val &= ~0x200000;
784  else
785  Val |= 0x200000;
786 
787  return Val;
788 }
789 
790 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
791 /// ADR label target.
792 uint32_t ARMMCCodeEmitter::
793 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
794  SmallVectorImpl<MCFixup> &Fixups,
795  const MCSubtargetInfo &STI) const {
796  const MCOperand MO = MI.getOperand(OpIdx);
797  if (MO.isExpr())
799  Fixups, STI);
800  int64_t offset = MO.getImm();
801  uint32_t Val = 0x2000;
802 
803  int SoImmVal;
804  if (offset == INT32_MIN) {
805  Val = 0x1000;
806  SoImmVal = 0;
807  } else if (offset < 0) {
808  Val = 0x1000;
809  offset *= -1;
810  SoImmVal = ARM_AM::getSOImmVal(offset);
811  if(SoImmVal == -1) {
812  Val = 0x2000;
813  offset *= -1;
814  SoImmVal = ARM_AM::getSOImmVal(offset);
815  }
816  } else {
817  SoImmVal = ARM_AM::getSOImmVal(offset);
818  if(SoImmVal == -1) {
819  Val = 0x1000;
820  offset *= -1;
821  SoImmVal = ARM_AM::getSOImmVal(offset);
822  }
823  }
824 
825  assert(SoImmVal != -1 && "Not a valid so_imm value!");
826 
827  Val |= SoImmVal;
828  return Val;
829 }
830 
831 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
832 /// target.
833 uint32_t ARMMCCodeEmitter::
834 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
835  SmallVectorImpl<MCFixup> &Fixups,
836  const MCSubtargetInfo &STI) const {
837  const MCOperand MO = MI.getOperand(OpIdx);
838  if (MO.isExpr())
840  Fixups, STI);
841  int32_t Val = MO.getImm();
842  if (Val == INT32_MIN)
843  Val = 0x1000;
844  else if (Val < 0) {
845  Val *= -1;
846  Val |= 0x1000;
847  }
848  return Val;
849 }
850 
851 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
852 /// target.
853 uint32_t ARMMCCodeEmitter::
854 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
855  SmallVectorImpl<MCFixup> &Fixups,
856  const MCSubtargetInfo &STI) const {
857  const MCOperand MO = MI.getOperand(OpIdx);
858  if (MO.isExpr())
860  Fixups, STI);
861  return MO.getImm();
862 }
863 
864 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
865 /// operand.
866 uint32_t ARMMCCodeEmitter::
867 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
869  const MCSubtargetInfo &STI) const {
870  // [Rn, Rm]
871  // {5-3} = Rm
872  // {2-0} = Rn
873  const MCOperand &MO1 = MI.getOperand(OpIdx);
874  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
875  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
876  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
877  return (Rm << 3) | Rn;
878 }
879 
880 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
881 uint32_t ARMMCCodeEmitter::
882 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
883  SmallVectorImpl<MCFixup> &Fixups,
884  const MCSubtargetInfo &STI) const {
885  // {17-13} = reg
886  // {12} = (U)nsigned (add == '1', sub == '0')
887  // {11-0} = imm12
888  unsigned Reg, Imm12;
889  bool isAdd = true;
890  // If The first operand isn't a register, we have a label reference.
891  const MCOperand &MO = MI.getOperand(OpIdx);
892  if (!MO.isReg()) {
893  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
894  Imm12 = 0;
895 
896  if (MO.isExpr()) {
897  const MCExpr *Expr = MO.getExpr();
898  isAdd = false ; // 'U' bit is set as part of the fixup.
899 
901  if (isThumb2(STI))
903  else
905  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
906 
907  ++MCNumCPRelocations;
908  } else {
909  Reg = ARM::PC;
910  int32_t Offset = MO.getImm();
911  if (Offset == INT32_MIN) {
912  Offset = 0;
913  isAdd = false;
914  } else if (Offset < 0) {
915  Offset *= -1;
916  isAdd = false;
917  }
918  Imm12 = Offset;
919  }
920  } else
921  isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
922 
923  uint32_t Binary = Imm12 & 0xfff;
924  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
925  if (isAdd)
926  Binary |= (1 << 12);
927  Binary |= (Reg << 13);
928  return Binary;
929 }
930 
931 /// getT2Imm8s4OpValue - Return encoding info for
932 /// '+/- imm8<<2' operand.
933 uint32_t ARMMCCodeEmitter::
934 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
935  SmallVectorImpl<MCFixup> &Fixups,
936  const MCSubtargetInfo &STI) const {
937  // FIXME: The immediate operand should have already been encoded like this
938  // before ever getting here. The encoder method should just need to combine
939  // the MI operands for the register and the offset into a single
940  // representation for the complex operand in the .td file. This isn't just
941  // style, unfortunately. As-is, we can't represent the distinct encoding
942  // for #-0.
943 
944  // {8} = (U)nsigned (add == '1', sub == '0')
945  // {7-0} = imm8
946  int32_t Imm8 = MI.getOperand(OpIdx).getImm();
947  bool isAdd = Imm8 >= 0;
948 
949  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
950  if (Imm8 < 0)
951  Imm8 = -(uint32_t)Imm8;
952 
953  // Scaled by 4.
954  Imm8 /= 4;
955 
956  uint32_t Binary = Imm8 & 0xff;
957  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
958  if (isAdd)
959  Binary |= (1 << 8);
960  return Binary;
961 }
962 
963 /// getT2AddrModeImm8s4OpValue - Return encoding info for
964 /// 'reg +/- imm8<<2' operand.
965 uint32_t ARMMCCodeEmitter::
966 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
967  SmallVectorImpl<MCFixup> &Fixups,
968  const MCSubtargetInfo &STI) const {
969  // {12-9} = reg
970  // {8} = (U)nsigned (add == '1', sub == '0')
971  // {7-0} = imm8
972  unsigned Reg, Imm8;
973  bool isAdd = true;
974  // If The first operand isn't a register, we have a label reference.
975  const MCOperand &MO = MI.getOperand(OpIdx);
976  if (!MO.isReg()) {
977  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
978  Imm8 = 0;
979  isAdd = false ; // 'U' bit is set as part of the fixup.
980 
981  assert(MO.isExpr() && "Unexpected machine operand type!");
982  const MCExpr *Expr = MO.getExpr();
984  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
985 
986  ++MCNumCPRelocations;
987  } else
988  isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
989 
990  // FIXME: The immediate operand should have already been encoded like this
991  // before ever getting here. The encoder method should just need to combine
992  // the MI operands for the register and the offset into a single
993  // representation for the complex operand in the .td file. This isn't just
994  // style, unfortunately. As-is, we can't represent the distinct encoding
995  // for #-0.
996  uint32_t Binary = (Imm8 >> 2) & 0xff;
997  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
998  if (isAdd)
999  Binary |= (1 << 8);
1000  Binary |= (Reg << 9);
1001  return Binary;
1002 }
1003 
1004 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1005 /// 'reg + imm8<<2' operand.
1006 uint32_t ARMMCCodeEmitter::
1007 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1008  SmallVectorImpl<MCFixup> &Fixups,
1009  const MCSubtargetInfo &STI) const {
1010  // {11-8} = reg
1011  // {7-0} = imm8
1012  const MCOperand &MO = MI.getOperand(OpIdx);
1013  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1014  unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1015  unsigned Imm8 = MO1.getImm();
1016  return (Reg << 8) | Imm8;
1017 }
1018 
1019 uint32_t
1020 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1021  SmallVectorImpl<MCFixup> &Fixups,
1022  const MCSubtargetInfo &STI) const {
1023  // {20-16} = imm{15-12}
1024  // {11-0} = imm{11-0}
1025  const MCOperand &MO = MI.getOperand(OpIdx);
1026  if (MO.isImm())
1027  // Hi / lo 16 bits already extracted during earlier passes.
1028  return static_cast<unsigned>(MO.getImm());
1029 
1030  // Handle :upper16: and :lower16: assembly prefixes.
1031  const MCExpr *E = MO.getExpr();
1032  MCFixupKind Kind;
1033  if (E->getKind() == MCExpr::Target) {
1034  const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1035  E = ARM16Expr->getSubExpr();
1036 
1037  if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1038  const int64_t Value = MCE->getValue();
1039  if (Value > UINT32_MAX)
1040  report_fatal_error("constant value truncated (limited to 32-bit)");
1041 
1042  switch (ARM16Expr->getKind()) {
1044  return (int32_t(Value) & 0xffff0000) >> 16;
1046  return (int32_t(Value) & 0x0000ffff);
1047  default: llvm_unreachable("Unsupported ARMFixup");
1048  }
1049  }
1050 
1051  switch (ARM16Expr->getKind()) {
1052  default: llvm_unreachable("Unsupported ARMFixup");
1056  break;
1060  break;
1061  }
1062 
1063  Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1064  return 0;
1065  }
1066  // If the expression doesn't have :upper16: or :lower16: on it,
1067  // it's just a plain immediate expression, previously those evaluated to
1068  // the lower 16 bits of the expression regardless of whether
1069  // we have a movt or a movw, but that led to misleadingly results.
1070  // This is disallowed in the AsmParser in validateInstruction()
1071  // so this should never happen.
1072  llvm_unreachable("expression without :upper16: or :lower16:");
1073 }
1074 
1075 uint32_t ARMMCCodeEmitter::
1076 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1077  SmallVectorImpl<MCFixup> &Fixups,
1078  const MCSubtargetInfo &STI) const {
1079  const MCOperand &MO = MI.getOperand(OpIdx);
1080  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1081  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1082  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1083  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1084  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1085  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1087  unsigned SBits = getShiftOp(ShOp);
1088 
1089  // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1090  // amount. However, it would be an easy mistake to make so check here.
1091  assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1092 
1093  // {16-13} = Rn
1094  // {12} = isAdd
1095  // {11-0} = shifter
1096  // {3-0} = Rm
1097  // {4} = 0
1098  // {6-5} = type
1099  // {11-7} = imm
1100  uint32_t Binary = Rm;
1101  Binary |= Rn << 13;
1102  Binary |= SBits << 5;
1103  Binary |= ShImm << 7;
1104  if (isAdd)
1105  Binary |= 1 << 12;
1106  return Binary;
1107 }
1108 
1109 uint32_t ARMMCCodeEmitter::
1110 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1111  SmallVectorImpl<MCFixup> &Fixups,
1112  const MCSubtargetInfo &STI) const {
1113  // {13} 1 == imm12, 0 == Rm
1114  // {12} isAdd
1115  // {11-0} imm12/Rm
1116  const MCOperand &MO = MI.getOperand(OpIdx);
1117  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1118  unsigned Imm = MO1.getImm();
1119  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1120  bool isReg = MO.getReg() != 0;
1121  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1122  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1123  if (isReg) {
1125  Binary <<= 7; // Shift amount is bits [11:7]
1126  Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1127  Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1128  }
1129  return Binary | (isAdd << 12) | (isReg << 13);
1130 }
1131 
1132 uint32_t ARMMCCodeEmitter::
1133 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1134  SmallVectorImpl<MCFixup> &Fixups,
1135  const MCSubtargetInfo &STI) const {
1136  // {4} isAdd
1137  // {3-0} Rm
1138  const MCOperand &MO = MI.getOperand(OpIdx);
1139  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1140  bool isAdd = MO1.getImm() != 0;
1141  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1142 }
1143 
1144 uint32_t ARMMCCodeEmitter::
1145 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1146  SmallVectorImpl<MCFixup> &Fixups,
1147  const MCSubtargetInfo &STI) const {
1148  // {9} 1 == imm8, 0 == Rm
1149  // {8} isAdd
1150  // {7-4} imm7_4/zero
1151  // {3-0} imm3_0/Rm
1152  const MCOperand &MO = MI.getOperand(OpIdx);
1153  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1154  unsigned Imm = MO1.getImm();
1155  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1156  bool isImm = MO.getReg() == 0;
1158  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1159  if (!isImm)
1160  Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1161  return Imm8 | (isAdd << 8) | (isImm << 9);
1162 }
1163 
1164 uint32_t ARMMCCodeEmitter::
1165 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1166  SmallVectorImpl<MCFixup> &Fixups,
1167  const MCSubtargetInfo &STI) const {
1168  // {13} 1 == imm8, 0 == Rm
1169  // {12-9} Rn
1170  // {8} isAdd
1171  // {7-4} imm7_4/zero
1172  // {3-0} imm3_0/Rm
1173  const MCOperand &MO = MI.getOperand(OpIdx);
1174  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1175  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1176 
1177  // If The first operand isn't a register, we have a label reference.
1178  if (!MO.isReg()) {
1179  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1180 
1181  assert(MO.isExpr() && "Unexpected machine operand type!");
1182  const MCExpr *Expr = MO.getExpr();
1184  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1185 
1186  ++MCNumCPRelocations;
1187  return (Rn << 9) | (1 << 13);
1188  }
1189  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1190  unsigned Imm = MO2.getImm();
1191  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1192  bool isImm = MO1.getReg() == 0;
1194  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1195  if (!isImm)
1196  Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1197  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1198 }
1199 
1200 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1201 uint32_t ARMMCCodeEmitter::
1202 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1203  SmallVectorImpl<MCFixup> &Fixups,
1204  const MCSubtargetInfo &STI) const {
1205  // [SP, #imm]
1206  // {7-0} = imm8
1207  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1208  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1209  "Unexpected base register!");
1210 
1211  // The immediate is already shifted for the implicit zeroes, so no change
1212  // here.
1213  return MO1.getImm() & 0xff;
1214 }
1215 
1216 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1217 uint32_t ARMMCCodeEmitter::
1218 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1219  SmallVectorImpl<MCFixup> &Fixups,
1220  const MCSubtargetInfo &STI) const {
1221  // [Rn, #imm]
1222  // {7-3} = imm5
1223  // {2-0} = Rn
1224  const MCOperand &MO = MI.getOperand(OpIdx);
1225  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1226  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1227  unsigned Imm5 = MO1.getImm();
1228  return ((Imm5 & 0x1f) << 3) | Rn;
1229 }
1230 
1231 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1232 uint32_t ARMMCCodeEmitter::
1233 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1234  SmallVectorImpl<MCFixup> &Fixups,
1235  const MCSubtargetInfo &STI) const {
1236  const MCOperand MO = MI.getOperand(OpIdx);
1237  if (MO.isExpr())
1239  return (MO.getImm() >> 2);
1240 }
1241 
1242 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1243 uint32_t ARMMCCodeEmitter::
1244 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1245  SmallVectorImpl<MCFixup> &Fixups,
1246  const MCSubtargetInfo &STI) const {
1247  // {12-9} = reg
1248  // {8} = (U)nsigned (add == '1', sub == '0')
1249  // {7-0} = imm8
1250  unsigned Reg, Imm8;
1251  bool isAdd;
1252  // If The first operand isn't a register, we have a label reference.
1253  const MCOperand &MO = MI.getOperand(OpIdx);
1254  if (!MO.isReg()) {
1255  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1256  Imm8 = 0;
1257  isAdd = false; // 'U' bit is handled as part of the fixup.
1258 
1259  assert(MO.isExpr() && "Unexpected machine operand type!");
1260  const MCExpr *Expr = MO.getExpr();
1261  MCFixupKind Kind;
1262  if (isThumb2(STI))
1264  else
1266  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1267 
1268  ++MCNumCPRelocations;
1269  } else {
1270  EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1271  isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1272  }
1273 
1274  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1275  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1276  if (isAdd)
1277  Binary |= (1 << 8);
1278  Binary |= (Reg << 9);
1279  return Binary;
1280 }
1281 
1282 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1283 uint32_t ARMMCCodeEmitter::
1284 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1285  SmallVectorImpl<MCFixup> &Fixups,
1286  const MCSubtargetInfo &STI) const {
1287  // {12-9} = reg
1288  // {8} = (U)nsigned (add == '1', sub == '0')
1289  // {7-0} = imm8
1290  unsigned Reg, Imm8;
1291  bool isAdd;
1292  // If The first operand isn't a register, we have a label reference.
1293  const MCOperand &MO = MI.getOperand(OpIdx);
1294  if (!MO.isReg()) {
1295  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1296  Imm8 = 0;
1297  isAdd = false; // 'U' bit is handled as part of the fixup.
1298 
1299  assert(MO.isExpr() && "Unexpected machine operand type!");
1300  const MCExpr *Expr = MO.getExpr();
1301  MCFixupKind Kind;
1302  if (isThumb2(STI))
1304  else
1306  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1307 
1308  ++MCNumCPRelocations;
1309  } else {
1310  EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1311  isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1312  }
1313 
1314  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1315  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1316  if (isAdd)
1317  Binary |= (1 << 8);
1318  Binary |= (Reg << 9);
1319  return Binary;
1320 }
1321 
1322 unsigned ARMMCCodeEmitter::
1323 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1324  SmallVectorImpl<MCFixup> &Fixups,
1325  const MCSubtargetInfo &STI) const {
1326  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1327  // shifted. The second is Rs, the amount to shift by, and the third specifies
1328  // the type of the shift.
1329  //
1330  // {3-0} = Rm.
1331  // {4} = 1
1332  // {6-5} = type
1333  // {11-8} = Rs
1334  // {7} = 0
1335 
1336  const MCOperand &MO = MI.getOperand(OpIdx);
1337  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1338  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1340 
1341  // Encode Rm.
1342  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1343 
1344  // Encode the shift opcode.
1345  unsigned SBits = 0;
1346  unsigned Rs = MO1.getReg();
1347  if (Rs) {
1348  // Set shift operand (bit[7:4]).
1349  // LSL - 0001
1350  // LSR - 0011
1351  // ASR - 0101
1352  // ROR - 0111
1353  switch (SOpc) {
1354  default: llvm_unreachable("Unknown shift opc!");
1355  case ARM_AM::lsl: SBits = 0x1; break;
1356  case ARM_AM::lsr: SBits = 0x3; break;
1357  case ARM_AM::asr: SBits = 0x5; break;
1358  case ARM_AM::ror: SBits = 0x7; break;
1359  }
1360  }
1361 
1362  Binary |= SBits << 4;
1363 
1364  // Encode the shift operation Rs.
1365  // Encode Rs bit[11:8].
1366  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1367  return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1368 }
1369 
1370 unsigned ARMMCCodeEmitter::
1371 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1372  SmallVectorImpl<MCFixup> &Fixups,
1373  const MCSubtargetInfo &STI) const {
1374  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1375  // shifted. The second is the amount to shift by.
1376  //
1377  // {3-0} = Rm.
1378  // {4} = 0
1379  // {6-5} = type
1380  // {11-7} = imm
1381 
1382  const MCOperand &MO = MI.getOperand(OpIdx);
1383  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1385 
1386  // Encode Rm.
1387  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1388 
1389  // Encode the shift opcode.
1390  unsigned SBits = 0;
1391 
1392  // Set shift operand (bit[6:4]).
1393  // LSL - 000
1394  // LSR - 010
1395  // ASR - 100
1396  // ROR - 110
1397  // RRX - 110 and bit[11:8] clear.
1398  switch (SOpc) {
1399  default: llvm_unreachable("Unknown shift opc!");
1400  case ARM_AM::lsl: SBits = 0x0; break;
1401  case ARM_AM::lsr: SBits = 0x2; break;
1402  case ARM_AM::asr: SBits = 0x4; break;
1403  case ARM_AM::ror: SBits = 0x6; break;
1404  case ARM_AM::rrx:
1405  Binary |= 0x60;
1406  return Binary;
1407  }
1408 
1409  // Encode shift_imm bit[11:7].
1410  Binary |= SBits << 4;
1411  unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1412  assert(Offset < 32 && "Offset must be in range 0-31!");
1413  return Binary | (Offset << 7);
1414 }
1415 
1416 
1417 unsigned ARMMCCodeEmitter::
1418 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1419  SmallVectorImpl<MCFixup> &Fixups,
1420  const MCSubtargetInfo &STI) const {
1421  const MCOperand &MO1 = MI.getOperand(OpNum);
1422  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1423  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1424 
1425  // Encoded as [Rn, Rm, imm].
1426  // FIXME: Needs fixup support.
1427  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1428  Value <<= 4;
1429  Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1430  Value <<= 2;
1431  Value |= MO3.getImm();
1432 
1433  return Value;
1434 }
1435 
1436 unsigned ARMMCCodeEmitter::
1437 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1438  SmallVectorImpl<MCFixup> &Fixups,
1439  const MCSubtargetInfo &STI) const {
1440  const MCOperand &MO1 = MI.getOperand(OpNum);
1441  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1442 
1443  // FIXME: Needs fixup support.
1444  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1445 
1446  // Even though the immediate is 8 bits long, we need 9 bits in order
1447  // to represent the (inverse of the) sign bit.
1448  Value <<= 9;
1449  int32_t tmp = (int32_t)MO2.getImm();
1450  if (tmp < 0)
1451  tmp = abs(tmp);
1452  else
1453  Value |= 256; // Set the ADD bit
1454  Value |= tmp & 255;
1455  return Value;
1456 }
1457 
1458 unsigned ARMMCCodeEmitter::
1459 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1460  SmallVectorImpl<MCFixup> &Fixups,
1461  const MCSubtargetInfo &STI) const {
1462  const MCOperand &MO1 = MI.getOperand(OpNum);
1463 
1464  // FIXME: Needs fixup support.
1465  unsigned Value = 0;
1466  int32_t tmp = (int32_t)MO1.getImm();
1467  if (tmp < 0)
1468  tmp = abs(tmp);
1469  else
1470  Value |= 256; // Set the ADD bit
1471  Value |= tmp & 255;
1472  return Value;
1473 }
1474 
1475 unsigned ARMMCCodeEmitter::
1476 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1477  SmallVectorImpl<MCFixup> &Fixups,
1478  const MCSubtargetInfo &STI) const {
1479  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1480  // shifted. The second is the amount to shift by.
1481  //
1482  // {3-0} = Rm.
1483  // {4} = 0
1484  // {6-5} = type
1485  // {11-7} = imm
1486 
1487  const MCOperand &MO = MI.getOperand(OpIdx);
1488  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1490 
1491  // Encode Rm.
1492  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1493 
1494  // Encode the shift opcode.
1495  unsigned SBits = 0;
1496  // Set shift operand (bit[6:4]).
1497  // LSL - 000
1498  // LSR - 010
1499  // ASR - 100
1500  // ROR - 110
1501  switch (SOpc) {
1502  default: llvm_unreachable("Unknown shift opc!");
1503  case ARM_AM::lsl: SBits = 0x0; break;
1504  case ARM_AM::lsr: SBits = 0x2; break;
1505  case ARM_AM::asr: SBits = 0x4; break;
1507  case ARM_AM::ror: SBits = 0x6; break;
1508  }
1509 
1510  Binary |= SBits << 4;
1511  if (SOpc == ARM_AM::rrx)
1512  return Binary;
1513 
1514  // Encode shift_imm bit[11:7].
1515  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1516 }
1517 
1518 unsigned ARMMCCodeEmitter::
1519 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1520  SmallVectorImpl<MCFixup> &Fixups,
1521  const MCSubtargetInfo &STI) const {
1522  // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1523  // msb of the mask.
1524  const MCOperand &MO = MI.getOperand(Op);
1525  uint32_t v = ~MO.getImm();
1526  uint32_t lsb = countTrailingZeros(v);
1527  uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1528  assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1529  return lsb | (msb << 5);
1530 }
1531 
1532 unsigned ARMMCCodeEmitter::
1533 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1534  SmallVectorImpl<MCFixup> &Fixups,
1535  const MCSubtargetInfo &STI) const {
1536  // VLDM/VSTM:
1537  // {12-8} = Vd
1538  // {7-0} = Number of registers
1539  //
1540  // LDM/STM:
1541  // {15-0} = Bitfield of GPRs.
1542  unsigned Reg = MI.getOperand(Op).getReg();
1543  bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1544  bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1545 
1546  unsigned Binary = 0;
1547 
1548  if (SPRRegs || DPRRegs) {
1549  // VLDM/VSTM
1550  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1551  unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1552  Binary |= (RegNo & 0x1f) << 8;
1553  if (SPRRegs)
1554  Binary |= NumRegs;
1555  else
1556  Binary |= NumRegs * 2;
1557  } else {
1558  const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1559  assert(std::is_sorted(MI.begin() + Op, MI.end(),
1560  [&](const MCOperand &LHS, const MCOperand &RHS) {
1561  return MRI.getEncodingValue(LHS.getReg()) <
1562  MRI.getEncodingValue(RHS.getReg());
1563  }));
1564 
1565  for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1566  unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1567  Binary |= 1 << RegNo;
1568  }
1569  }
1570 
1571  return Binary;
1572 }
1573 
1574 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1575 /// with the alignment operand.
1576 unsigned ARMMCCodeEmitter::
1577 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1578  SmallVectorImpl<MCFixup> &Fixups,
1579  const MCSubtargetInfo &STI) const {
1580  const MCOperand &Reg = MI.getOperand(Op);
1581  const MCOperand &Imm = MI.getOperand(Op + 1);
1582 
1583  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1584  unsigned Align = 0;
1585 
1586  switch (Imm.getImm()) {
1587  default: break;
1588  case 2:
1589  case 4:
1590  case 8: Align = 0x01; break;
1591  case 16: Align = 0x02; break;
1592  case 32: Align = 0x03; break;
1593  }
1594 
1595  return RegNo | (Align << 4);
1596 }
1597 
1598 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1599 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1600 unsigned ARMMCCodeEmitter::
1601 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1602  SmallVectorImpl<MCFixup> &Fixups,
1603  const MCSubtargetInfo &STI) const {
1604  const MCOperand &Reg = MI.getOperand(Op);
1605  const MCOperand &Imm = MI.getOperand(Op + 1);
1606 
1607  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1608  unsigned Align = 0;
1609 
1610  switch (Imm.getImm()) {
1611  default: break;
1612  case 8:
1613  case 16:
1614  case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1615  case 2: Align = 0x00; break;
1616  case 4: Align = 0x03; break;
1617  }
1618 
1619  return RegNo | (Align << 4);
1620 }
1621 
1622 
1623 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1624 /// alignment operand for use in VLD-dup instructions. This is the same as
1625 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1626 /// different for VLD4-dup.
1627 unsigned ARMMCCodeEmitter::
1628 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1629  SmallVectorImpl<MCFixup> &Fixups,
1630  const MCSubtargetInfo &STI) const {
1631  const MCOperand &Reg = MI.getOperand(Op);
1632  const MCOperand &Imm = MI.getOperand(Op + 1);
1633 
1634  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1635  unsigned Align = 0;
1636 
1637  switch (Imm.getImm()) {
1638  default: break;
1639  case 2:
1640  case 4:
1641  case 8: Align = 0x01; break;
1642  case 16: Align = 0x03; break;
1643  }
1644 
1645  return RegNo | (Align << 4);
1646 }
1647 
1648 unsigned ARMMCCodeEmitter::
1649 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1650  SmallVectorImpl<MCFixup> &Fixups,
1651  const MCSubtargetInfo &STI) const {
1652  const MCOperand &MO = MI.getOperand(Op);
1653  if (MO.getReg() == 0) return 0x0D;
1654  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1655 }
1656 
1657 unsigned ARMMCCodeEmitter::
1658 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1659  SmallVectorImpl<MCFixup> &Fixups,
1660  const MCSubtargetInfo &STI) const {
1661  return 8 - MI.getOperand(Op).getImm();
1662 }
1663 
1664 unsigned ARMMCCodeEmitter::
1665 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1666  SmallVectorImpl<MCFixup> &Fixups,
1667  const MCSubtargetInfo &STI) const {
1668  return 16 - MI.getOperand(Op).getImm();
1669 }
1670 
1671 unsigned ARMMCCodeEmitter::
1672 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1673  SmallVectorImpl<MCFixup> &Fixups,
1674  const MCSubtargetInfo &STI) const {
1675  return 32 - MI.getOperand(Op).getImm();
1676 }
1677 
1678 unsigned ARMMCCodeEmitter::
1679 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1680  SmallVectorImpl<MCFixup> &Fixups,
1681  const MCSubtargetInfo &STI) const {
1682  return 64 - MI.getOperand(Op).getImm();
1683 }
1684 
1685 void ARMMCCodeEmitter::
1686 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1687  SmallVectorImpl<MCFixup> &Fixups,
1688  const MCSubtargetInfo &STI) const {
1689  // Pseudo instructions don't get encoded.
1690  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1691  uint64_t TSFlags = Desc.TSFlags;
1692  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1693  return;
1694 
1695  int Size;
1696  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1697  Size = Desc.getSize();
1698  else
1699  llvm_unreachable("Unexpected instruction size!");
1700 
1701  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1702  // Thumb 32-bit wide instructions need to emit the high order halfword
1703  // first.
1704  if (isThumb(STI) && Size == 4) {
1705  EmitConstant(Binary >> 16, 2, OS);
1706  EmitConstant(Binary & 0xffff, 2, OS);
1707  } else
1708  EmitConstant(Binary, Size, OS);
1709  ++MCNumEmitted; // Keep track of the # of mi's emitted.
1710 }
1711 
1712 #include "ARMGenMCCodeEmitter.inc"
1713 
1715  const MCRegisterInfo &MRI,
1716  MCContext &Ctx) {
1717  return new ARMMCCodeEmitter(MCII, Ctx, true);
1718 }
1719 
1721  const MCRegisterInfo &MRI,
1722  MCContext &Ctx) {
1723  return new ARMMCCodeEmitter(MCII, Ctx, false);
1724 }
static bool isReg(const MCInst &MI, unsigned OpNo)
uint64_t CallInst * C
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Definition: MCInst.h:193
iterator begin()
Definition: MCInst.h:191
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool isImm() const
Definition: MCInst.h:58
unsigned getSOImmValImm(unsigned Imm)
getSOImmValImm - Given an encoded imm field for the reg/imm form, return the 8-bit imm value...
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LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
VariantKind getKind() const
getOpcode - Get the kind of this expression.
Definition: ARMMCExpr.h:51
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
bool isReg() const
Definition: MCInst.h:57
STATISTIC(NumFunctions, "Total number of functions")
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:188
static Lanai::Fixups FixupKind(const MCExpr *Expr)
static bool isThumb(const MCSubtargetInfo &STI)
const Triple & getTargetTriple() const
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
A four-byte fixup.
Definition: MCFixup.h:25
Context object for machine code objects.
Definition: MCContext.h:62
unsigned char getAM3Offset(unsigned AM3Opc)
const MCExpr * getExpr() const
Definition: MCInst.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
AddrOpc getAM2Op(unsigned AM2Opc)
int64_t getImm() const
Definition: MCInst.h:75
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
unsigned getSORegOffset(unsigned Op)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isFPImm() const
Definition: MCInst.h:59
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
This file declares a class to represent arbitrary precision floating point values and provide a varie...
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
bool isExpr() const
Definition: MCInst.h:60
unsigned getSOImmValRot(unsigned Imm)
getSOImmValRot - Given an encoded imm field for the reg/imm form, return the rotate amount...
unsigned getNumOperands() const
Definition: MCInst.h:181
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:618
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:89
static int32_t encodeThumbBLOffset(int32_t offset)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ExprKind getKind() const
Definition: MCExpr.h:72
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
unsigned getAM2Offset(unsigned AM2Opc)
SMLoc getLoc() const
Definition: MCInst.h:177
ShiftOpc getSORegShOp(unsigned Op)
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: ARMMCExpr.h:54
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1212
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
LLVM Value Representation.
Definition: Value.h:72
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
Target specific expression.
Definition: MCExpr.h:42
AddrOpc getAM5Op(unsigned AM5Opc)
unsigned getOpcode() const
Definition: MCInst.h:171
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Function Alias Analysis false
double getFPImm() const
Definition: MCInst.h:85
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:580