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SIFrameLowering.h
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1 //===--------------------- SIFrameLowering.h --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
10 #define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
11 
12 #include "AMDGPUFrameLowering.h"
13 
14 namespace llvm {
15 
16 class SIInstrInfo;
17 class SIMachineFunctionInfo;
18 class SIRegisterInfo;
19 class GCNSubtarget;
20 
21 class SIFrameLowering final : public AMDGPUFrameLowering {
22 public:
24  Align TransAl = Align::None())
25  : AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
26  ~SIFrameLowering() override = default;
27 
29  MachineBasicBlock &MBB) const;
31  MachineBasicBlock &MBB) const override;
33  MachineBasicBlock &MBB) const override;
34  int getFrameIndexReference(const MachineFunction &MF, int FI,
35  unsigned &FrameReg) const override;
36 
37  void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
38  RegScavenger *RS = nullptr) const override;
40  RegScavenger *RS = nullptr) const;
41  bool
43  const TargetRegisterInfo *TRI,
44  std::vector<CalleeSavedInfo> &CSI) const override;
45 
46  bool isSupportedStackID(TargetStackID::Value ID) const override;
47 
49  MachineFunction &MF,
50  RegScavenger *RS = nullptr) const override;
51 
54  MachineBasicBlock &MBB,
55  MachineBasicBlock::iterator MI) const override;
56 
57 private:
58  void emitFlatScratchInit(const GCNSubtarget &ST,
59  MachineFunction &MF,
60  MachineBasicBlock &MBB) const;
61 
62  unsigned getReservedPrivateSegmentBufferReg(
63  const GCNSubtarget &ST,
64  const SIInstrInfo *TII,
65  const SIRegisterInfo *TRI,
67  MachineFunction &MF) const;
68 
69  std::pair<unsigned, bool> getReservedPrivateSegmentWaveByteOffsetReg(
70  const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI,
71  SIMachineFunctionInfo *MFI, MachineFunction &MF) const;
72 
73  // Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set.
74  void emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF,
76  MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg,
77  unsigned ScratchRsrcReg) const;
78 
79 public:
80  bool hasFP(const MachineFunction &MF) const override;
81 };
82 
83 } // end namespace llvm
84 
85 #endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
~SIFrameLowering() override=default
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
void emitEntryFunctionPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const
unsigned const TargetRegisterInfo * TRI
bool isSupportedStackID(TargetStackID::Value ID) const override
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
const HexagonInstrInfo * TII
Interface to describe a layout of a stack frame on an AMDGPU target.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
static constexpr const Align None()
Returns a default constructed Align which corresponds to no alignment.
Definition: Alignment.h:93
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
void determineCalleeSavesSGPR(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
SIFrameLowering(StackDirection D, Align StackAl, int LAO, Align TransAl=Align::None())
Information about the stack frame layout on the AMDGPU targets.
#define I(x, y, z)
Definition: MD5.cpp:58
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
IRTranslator LLVM IR MI
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...