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SIFrameLowering.h
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1 //===--------------------- SIFrameLowering.h --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
10 #define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
11 
12 #include "AMDGPUFrameLowering.h"
13 
14 namespace llvm {
15 
16 class SIInstrInfo;
17 class SIMachineFunctionInfo;
18 class SIRegisterInfo;
19 class GCNSubtarget;
20 
21 class SIFrameLowering final : public AMDGPUFrameLowering {
22 public:
23  SIFrameLowering(StackDirection D, unsigned StackAl, int LAO,
24  unsigned TransAl = 1) :
25  AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
26  ~SIFrameLowering() override = default;
27 
29  MachineBasicBlock &MBB) const;
31  MachineBasicBlock &MBB) const override;
33  MachineBasicBlock &MBB) const override;
34  int getFrameIndexReference(const MachineFunction &MF, int FI,
35  unsigned &FrameReg) const override;
36 
37  void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
38  RegScavenger *RS = nullptr) const override;
39 
41  MachineFunction &MF,
42  RegScavenger *RS = nullptr) const override;
43 
46  MachineBasicBlock &MBB,
47  MachineBasicBlock::iterator MI) const override;
48 
49 private:
50  void emitFlatScratchInit(const GCNSubtarget &ST,
51  MachineFunction &MF,
52  MachineBasicBlock &MBB) const;
53 
54  unsigned getReservedPrivateSegmentBufferReg(
55  const GCNSubtarget &ST,
56  const SIInstrInfo *TII,
57  const SIRegisterInfo *TRI,
59  MachineFunction &MF) const;
60 
61  std::pair<unsigned, unsigned> getReservedPrivateSegmentWaveByteOffsetReg(
62  const GCNSubtarget &ST,
63  const SIInstrInfo *TII,
64  const SIRegisterInfo *TRI,
66  MachineFunction &MF) const;
67 
68  // Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set.
69  void emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF,
71  MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg,
72  unsigned ScratchRsrcReg) const;
73 
74 public:
75  bool hasFP(const MachineFunction &MF) const override;
76  bool hasSP(const MachineFunction &MF) const;
77 };
78 
79 } // end namespace llvm
80 
81 #endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
~SIFrameLowering() override=default
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
void emitEntryFunctionPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const
unsigned const TargetRegisterInfo * TRI
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
const HexagonInstrInfo * TII
Interface to describe a layout of a stack frame on an AMDGPU target.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
SIFrameLowering(StackDirection D, unsigned StackAl, int LAO, unsigned TransAl=1)
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Information about the stack frame layout on the AMDGPU targets.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasSP(const MachineFunction &MF) const
IRTranslator LLVM IR MI
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...