LLVM 24.0.0git
GCNPreRAAntiHints.h
Go to the documentation of this file.
1//===- GCNPreRAAntiHints.h --------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_GCNPRERAANTIHINTS_H
10#define LLVM_LIB_TARGET_AMDGPU_GCNPRERAANTIHINTS_H
11
14
15namespace llvm {
16
17class MachineFunction;
18class MachineInstr;
20class LiveIntervals;
21class SIRegisterInfo;
22class SIInstrInfo;
23class GCNSubtarget;
25
26namespace AMDGPU {
27
29namespace HazardClass {
30
31// Coherent with CoExec instruction types
32enum : HazardClassMask {
33 None = 0,
34 CTRL = 1u << 0,
35 VALU = 1u << 1,
36 TRANS = 1u << 2,
37 SALU = 1u << 3,
38 DS = 1u << 4,
39 VMEM = 1u << 5,
40 SMEM = 1u << 6,
41 WMMA = 1u << 7,
42 MFMA = 1u << 8,
43 EXP = 1u << 9,
44};
45} // namespace HazardClass
46
58
63
72
73struct ClassMatch {
75 bool matches(HazardClassMask Mask) const { return !AnyOf || (Mask & AnyOf); }
76};
77
78// To enable or disable the whole rule.
79using RulePredicate = bool (*)(const HazardContext &);
80
81// To gate the rule for producer or consumer.
82using InstPredicate = bool (*)(const MachineInstr &, const HazardContext &);
83
84// This helps advancing a window for the WAW/WAR case where a RAW sits between
85// the producer and the consumer.
86using AdvanceForRawWindowFn = unsigned (*)(const MachineInstr &Producer,
87 HazardClassMask ReaderClass,
88 const HazardContext &Ctx);
89
95
96// Length of a hazard window in wait states.
97// Precedence: OptWindowLength --> Fn --> WindowLength.
98struct WindowSpec {
99 unsigned WindowLength = 0;
101 unsigned (*Fn)(const MachineInstr &Producer,
102 const HazardContext &Ctx) = nullptr;
103};
104
111
118
120
121} // namespace AMDGPU
122} // namespace llvm
123
124#endif // LLVM_LIB_TARGET_AMDGPU_GCNPRERAANTIHINTS_H
This file defines the SmallVector class.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Provide an instruction scheduling machine model to CodeGen passes.
uint32_t HazardClassMask
bool(*)(const HazardContext &) RulePredicate
void applyAntiHintRules(MachineFunction &MF, const HazardContext &Ctx)
unsigned(*)(const MachineInstr &Producer, HazardClassMask ReaderClass, const HazardContext &Ctx) AdvanceForRawWindowFn
bool(*)(const MachineInstr &, const HazardContext &) InstPredicate
This is an optimization pass for GlobalISel generic memory operations.
bool matches(HazardClassMask Mask) const
SmallVector< ConsumerTarget, 3 > Consumers
AdvanceForRawWindowFn AdvanceForRawWindow
const SIRegisterInfo * TRI
MachineRegisterInfo * MRI
const TargetSchedModel * SchedModel
unsigned(* Fn)(const MachineInstr &Producer, const HazardContext &Ctx)
const cl::opt< unsigned > * OptWindowLength