LLVM 20.0.0git
LoongArchDisassembler.cpp
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1//===-- LoongArchDisassembler.cpp - Disassembler for LoongArch ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the LoongArchDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
16#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/Support/Endian.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "loongarch-disassembler"
29
31
32namespace {
33class LoongArchDisassembler : public MCDisassembler {
34public:
35 LoongArchDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
36 : MCDisassembler(STI, Ctx) {}
37
39 ArrayRef<uint8_t> Bytes, uint64_t Address,
40 raw_ostream &CStream) const override;
41};
42} // end namespace
43
45 const MCSubtargetInfo &STI,
46 MCContext &Ctx) {
47 return new LoongArchDisassembler(STI, Ctx);
48}
49
51 // Register the disassembler for each target.
56}
57
59 uint64_t Address,
60 const MCDisassembler *Decoder) {
61 if (RegNo >= 32)
63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo));
65}
66
68 uint64_t Address,
69 const MCDisassembler *Decoder) {
70 if (RegNo >= 32)
72 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo));
74}
75
77 uint64_t Address,
78 const MCDisassembler *Decoder) {
79 if (RegNo >= 32)
81 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo));
83}
84
86 uint64_t Address,
87 const MCDisassembler *Decoder) {
88 if (RegNo >= 8)
90 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo));
92}
93
95 uint64_t Address,
96 const MCDisassembler *Decoder) {
97 if (RegNo >= 4)
99 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo));
101}
102
104 uint64_t Address,
105 const MCDisassembler *Decoder) {
106 if (RegNo >= 32)
108 Inst.addOperand(MCOperand::createReg(LoongArch::VR0 + RegNo));
110}
111
113 uint64_t Address,
114 const MCDisassembler *Decoder) {
115 if (RegNo >= 32)
117 Inst.addOperand(MCOperand::createReg(LoongArch::XR0 + RegNo));
119}
120
122 uint64_t Address,
123 const MCDisassembler *Decoder) {
124 if (RegNo >= 4)
126 Inst.addOperand(MCOperand::createReg(LoongArch::SCR0 + RegNo));
128}
129
130template <unsigned N, int P = 0>
132 int64_t Address,
133 const MCDisassembler *Decoder) {
134 assert(isUInt<N>(Imm) && "Invalid immediate");
135 Inst.addOperand(MCOperand::createImm(Imm + P));
137}
138
139template <unsigned N, unsigned S = 0>
141 int64_t Address,
142 const MCDisassembler *Decoder) {
143 assert(isUInt<N>(Imm) && "Invalid immediate");
144 // Shift left Imm <S> bits, then sign-extend the number in the bottom <N+S>
145 // bits.
146 Inst.addOperand(MCOperand::createImm(SignExtend64<N + S>(Imm << S)));
148}
149
150#include "LoongArchGenDisassemblerTables.inc"
151
152DecodeStatus LoongArchDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
153 ArrayRef<uint8_t> Bytes,
154 uint64_t Address,
155 raw_ostream &CS) const {
158
159 // We want to read exactly 4 bytes of data because all LoongArch instructions
160 // are fixed 32 bits.
161 if (Bytes.size() < 4) {
162 Size = 0;
164 }
165
167 // Calling the auto-generated decoder function.
168 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
169 Size = 4;
170
171 return Result;
172}
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:131
uint64_t Size
IRTranslator LLVM IR MI
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeSCRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCFRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLASX256RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLSX128RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchDisassembler()
static MCDisassembler * createLoongArchDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFCSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
const T * data() const
Definition: ArrayRef.h:162
Context object for machine code objects.
Definition: MCContext.h:83
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint32_t read32le(const void *P)
Definition: Endian.h:425
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheLoongArch64Target()
Target & getTheLoongArch32Target()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.