21#define GET_INSTRINFO_CTOR_DTOR
22#include "SPIRVGenInstrInfo.inc"
29 switch (
MI.getOpcode()) {
30 case SPIRV::OpConstantTrue:
31 case SPIRV::OpConstantFalse:
32 case SPIRV::OpConstantI:
33 case SPIRV::OpConstantF:
34 case SPIRV::OpConstantComposite:
35 case SPIRV::OpConstantSampler:
36 case SPIRV::OpConstantNull:
37 case SPIRV::OpSpecConstantTrue:
38 case SPIRV::OpSpecConstantFalse:
39 case SPIRV::OpSpecConstant:
40 case SPIRV::OpSpecConstantComposite:
41 case SPIRV::OpSpecConstantOp:
43 case SPIRV::OpConstantFunctionPointerINTEL:
51 switch (
MI.getOpcode()) {
52 case SPIRV::OpAsmTargetINTEL:
53 case SPIRV::OpAsmINTEL:
61 auto &
MRI =
MI.getMF()->getRegInfo();
62 if (
MI.getNumDefs() >= 1 &&
MI.getOperand(0).isReg()) {
63 auto DefRegClass =
MRI.getRegClassOrNull(
MI.getOperand(0).getReg());
64 return DefRegClass && DefRegClass->getID() == SPIRV::TYPERegClass.getID();
66 return MI.getOpcode() == SPIRV::OpTypeForwardPointer;
71 switch (
MI.getOpcode()) {
72 case SPIRV::OpDecorate:
73 case SPIRV::OpDecorateId:
74 case SPIRV::OpDecorateString:
75 case SPIRV::OpMemberDecorate:
76 case SPIRV::OpMemberDecorateString:
84 switch (
MI.getOpcode()) {
85 case SPIRV::OpCapability:
86 case SPIRV::OpExtension:
87 case SPIRV::OpExtInstImport:
88 case SPIRV::OpMemoryModel:
89 case SPIRV::OpEntryPoint:
90 case SPIRV::OpExecutionMode:
91 case SPIRV::OpExecutionModeId:
93 case SPIRV::OpSourceExtension:
95 case SPIRV::OpSourceContinued:
97 case SPIRV::OpMemberName:
98 case SPIRV::OpModuleProcessed:
106 switch (
MI.getOpcode()) {
125 switch (
MI.getOpcode()) {
132 case SPIRV::OpShiftLeftLogicalS:
133 case SPIRV::OpShiftLeftLogicalV:
134 case SPIRV::OpSNegate:
142 switch (
MI.getOpcode()) {
186 bool AllowModify)
const {
194 if (
MI->getOpcode() == SPIRV::OpBranch) {
195 TBB =
MI->getOperand(0).getMBB();
197 }
else if (
MI->getOpcode() == SPIRV::OpBranchConditional) {
198 Cond.push_back(
MI->getOperand(0));
199 TBB =
MI->getOperand(1).getMBB();
200 if (
MI->getNumOperands() == 3) {
201 FBB =
MI->getOperand(2).getMBB();
215 int *BytesRemoved)
const {
217 " to OpPhi instructions. Try using -O0 instead.");
237 "propagated to OpPhi instructions. Try using "
249 assert(
I->isCopy() &&
"Copy instruction is expected");
250 auto DstOp =
I->getOperand(0);
251 auto SrcOp =
I->getOperand(1);
253 "Register operands are expected in COPY");
254 auto &
MRI =
I->getMF()->getRegInfo();
259 if (
MI.getOpcode() == SPIRV::GET_ID ||
MI.getOpcode() == SPIRV::GET_ID64 ||
260 MI.getOpcode() == SPIRV::GET_fID ||
MI.getOpcode() == SPIRV::GET_fID64 ||
261 MI.getOpcode() == SPIRV::GET_pID32 ||
262 MI.getOpcode() == SPIRV::GET_pID64 ||
MI.getOpcode() == SPIRV::GET_vfID ||
263 MI.getOpcode() == SPIRV::GET_vID ||
MI.getOpcode() == SPIRV::GET_vpID32 ||
264 MI.getOpcode() == SPIRV::GET_vpID64) {
265 auto &
MRI =
MI.getMF()->getRegInfo();
266 MRI.replaceRegWith(
MI.getOperand(0).getReg(),
MI.getOperand(1).getReg());
267 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares the MachineIRBuilder class.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Wrapper class representing physical registers. Should be passed by value.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Representation of each machine instruction.
bool isConstantInstr(const MachineInstr &MI) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool isInlineAsmDefInstr(const MachineInstr &MI) const
bool isTypeDeclInstr(const MachineInstr &MI) const
bool canUseFastMathFlags(const MachineInstr &MI) const
bool isDecorationInstr(const MachineInstr &MI) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isHeaderInstr(const MachineInstr &MI) const
bool canUseNUW(const MachineInstr &MI) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool canUseNSW(const MachineInstr &MI) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is an optimization pass for GlobalISel generic memory operations.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.