14#ifndef LLVM_MCA_HARDWAREUNITS_SCHEDULER_H
15#define LLVM_MCA_HARDWAREUNITS_SCHEDULER_H
43 int computeRank(
const InstRef &Lhs)
const {
52 int LhsRank = computeRank(Lhs);
53 int RhsRank = computeRank(Rhs);
57 if (LhsRank == RhsRank)
59 return LhsRank < RhsRank;
74 std::unique_ptr<SchedulerStrategy> Strategy;
77 std::unique_ptr<ResourceManager> Resources;
111 std::vector<InstRef> WaitSet;
112 std::vector<InstRef> PendingSet;
113 std::vector<InstRef> ReadySet;
114 std::vector<InstRef> IssuedSet;
125 unsigned NumDispatchedToThePendingSet;
134 void initializeStrategy(std::unique_ptr<SchedulerStrategy> S);
137 void issueInstructionImpl(
161 std::unique_ptr<SchedulerStrategy> SelectStrategy)
166 std::unique_ptr<SchedulerStrategy> SelectStrategy)
167 : LSU(Lsu), Resources(
std::
move(RM)), BusyResourceUnits(0),
168 NumDispatchedToThePendingSet(0), HadTokenStall(
false) {
169 initializeStrategy(std::move(SelectStrategy));
235 return Resources->resolveResourceMask(Mask);
This file defines a base class for describing a simulated hardware unit.
A Load/Store unit class that models load/store queues and that implements a simple weak memory consis...
Legalize the Machine IR a function s Machine IR
The classes here represent processor resource units and their management strategy.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Default instruction selection strategy used by class Scheduler.
virtual ~DefaultSchedulerStrategy()
DefaultSchedulerStrategy()=default
bool compare(const InstRef &Lhs, const InstRef &Rhs) const override
Returns true if Lhs should take priority over Rhs.
An InstRef contains both a SourceMgr index and Instruction pair.
Instruction * getInstruction()
unsigned getSourceIndex() const
unsigned getNumUsers() const
Abstract base interface for LS (load/store) units in llvm-mca.
A resource manager for processor resource units and groups.
SchedulerStrategy()=default
virtual ~SchedulerStrategy()
virtual bool compare(const InstRef &Lhs, const InstRef &Rhs) const =0
Returns true if Lhs should take priority over Rhs.
Class Scheduler is responsible for issuing instructions to pipeline resources.
@ SC_DISPATCH_GROUP_STALL
InstRef select()
Select the next instruction to issue from the ReadySet.
unsigned getResourceID(uint64_t Mask) const
Convert a resource mask into a valid llvm processor resource identifier.
void issueInstruction(InstRef &IR, SmallVectorImpl< std::pair< ResourceRef, ReleaseAtCycles > > &Used, SmallVectorImpl< InstRef > &Pending, SmallVectorImpl< InstRef > &Ready)
Issue an instruction and populates a vector of used pipeline resources, and a vector of instructions ...
Scheduler(std::unique_ptr< ResourceManager > RM, LSUnitBase &Lsu, std::unique_ptr< SchedulerStrategy > SelectStrategy)
Status isAvailable(const InstRef &IR)
Check if the instruction in 'IR' can be dispatched during this cycle.
void analyzeDataDependencies(SmallVectorImpl< InstRef > &RegDeps, SmallVectorImpl< InstRef > &MemDeps)
This method is called by the ExecuteStage at the end of each cycle to identify bottlenecks caused by ...
Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu, std::unique_ptr< SchedulerStrategy > SelectStrategy)
bool dispatch(InstRef &IR)
Reserves buffer and LSUnit queue resources that are necessary to issue this instruction.
void cycleEvent(SmallVectorImpl< ResourceRef > &Freed, SmallVectorImpl< InstRef > &Executed, SmallVectorImpl< InstRef > &Pending, SmallVectorImpl< InstRef > &Ready)
This routine notifies the Scheduler that a new cycle just started.
bool mustIssueImmediately(const InstRef &IR) const
Returns true if IR has to be issued immediately, or if IR is a zero latency instruction.
uint64_t analyzeResourcePressure(SmallVectorImpl< InstRef > &Insts)
Returns a mask of busy resources, and populates vector Insts with instructions that could not be issu...
bool isReadySetEmpty() const
void instructionCheck(const InstRef &IR) const
Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu)
bool hadTokenStall() const
bool isWaitSetEmpty() const
Helper functions used by various pipeline components.
This is an optimization pass for GlobalISel generic memory operations.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Implement std::hash so that hash_code can be used in STL containers.
Machine model for scheduling, bundling, and heuristics.