SparcSubtarget.h

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//===-- SparcSubtarget.h - Define Subtarget for the SPARC -------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file declares the SPARC specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//
 
#ifndef LLVM_LIB_TARGET_SPARC_SPARCSUBTARGET_H
#define LLVM_LIB_TARGET_SPARC_SPARCSUBTARGET_H
 
#include "MCTargetDesc/SparcMCTargetDesc.h"
#include "SparcFrameLowering.h"
#include "SparcISelLowering.h"
#include "SparcInstrInfo.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TargetParser/Triple.h"
#include <string>
 
#define GET_SUBTARGETINFO_HEADER
#include "SparcGenSubtargetInfo.inc"
 
namespace llvm {
class StringRef;
 
class SparcSubtarget : public SparcGenSubtargetInfo {
  // ReserveRegister[i] - Register #i is not available as a general purpose
  // register.
  BitVector ReserveRegister;
 
  Triple TargetTriple;
  virtual void anchor();
 
  bool Is64Bit;
 
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER)                    \
  bool ATTRIBUTE = DEFAULT;
#include "SparcGenSubtargetInfo.inc"
 
  SparcInstrInfo InstrInfo;
  SparcTargetLowering TLInfo;
  SelectionDAGTargetInfo TSInfo;
  SparcFrameLowering FrameLowering;
 
public:
  SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU,
                 const StringRef &FS, const TargetMachine &TM, bool is64bit);
 
  const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; }
  const TargetFrameLowering *getFrameLowering() const override {
    return &FrameLowering;
  }
  const SparcRegisterInfo *getRegisterInfo() const override {
    return &InstrInfo.getRegisterInfo();
  }
  const SparcTargetLowering *getTargetLowering() const override {
    return &TLInfo;
  }
  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
    return &TSInfo;
  }
 
  bool enableMachineScheduler() const override;
 
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER)                    \
  bool GETTER() const { return ATTRIBUTE; }
#include "SparcGenSubtargetInfo.inc"
 
  /// ParseSubtargetFeatures - Parses features string setting specified
  /// subtarget options.  Definition of function is auto generated by tblgen.
  void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
  SparcSubtarget &initializeSubtargetDependencies(StringRef CPU,
                                                  StringRef TuneCPU,
                                                  StringRef FS);
 
  bool is64Bit() const { return Is64Bit; }
 
  /// The 64-bit ABI uses biased stack and frame pointers, so the stack frame
  /// of the current function is the area from [%sp+BIAS] to [%fp+BIAS].
  int64_t getStackPointerBias() const {
    return is64Bit() ? 2047 : 0;
  }
 
  bool isRegisterReserved(MCPhysReg PhysReg) const {
    return ReserveRegister[PhysReg];
  }
 
  /// Given a actual stack size as determined by FrameInfo, this function
  /// returns adjusted framesize which includes space for register window
  /// spills and arguments.
  int getAdjustedFrameSize(int stackSize) const;
 
  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
};
 
} // end namespace llvm
 
#endif