25#define GET_INSTRMAP_INFO
26#include "XtensaGenInstrInfo.inc"
27#undef GET_INSTRMAP_INFO
31#define DEBUG_TYPE "mccodeemitter"
41 : MCII(mcii), Ctx(ctx), IsLittleEndian(isLE) {}
43 ~XtensaMCCodeEmitter() {}
122 return new XtensaMCCodeEmitter(MCII, Ctx,
true);
125void XtensaMCCodeEmitter::encodeInstruction(
const MCInst &
MI,
129 uint64_t Bits = getBinaryCodeForInstr(
MI, Fixups, STI);
130 unsigned Size = MCII.get(
MI.getOpcode()).getSize();
132 if (IsLittleEndian) {
134 unsigned ShiftValue = 0;
135 for (
unsigned I = 0;
I !=
Size; ++
I) {
150 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
161XtensaMCCodeEmitter::getJumpTargetEncoding(
const MCInst &
MI,
unsigned int OpNum,
175uint32_t XtensaMCCodeEmitter::getBranchTargetEncoding(
183 switch (
MI.getOpcode()) {
199XtensaMCCodeEmitter::getCallEncoding(
const MCInst &
MI,
unsigned int OpNum,
204 int32_t Res = MO.
getImm();
220XtensaMCCodeEmitter::getL32RTargetEncoding(
const MCInst &
MI,
unsigned OpNum,
225 int32_t Res = MO.
getImm();
240XtensaMCCodeEmitter::getMemRegEncoding(
const MCInst &
MI,
unsigned OpNo,
243 assert(
MI.getOperand(OpNo + 1).isImm());
247 switch (
MI.getOpcode()) {
265 assert((isUInt<8>(Res)) &&
"Unexpected operand value!");
268 uint32_t RegBits = getMachineOpValue(
MI,
MI.getOperand(OpNo), Fixups, STI);
270 return ((OffBits & 0xFF0) | RegBits);
273uint32_t XtensaMCCodeEmitter::getImm8OpValue(
const MCInst &
MI,
unsigned OpNo,
277 int32_t Res = MO.
getImm();
279 assert(((Res >= -128) && (Res <= 127)) &&
"Unexpected operand value!");
285XtensaMCCodeEmitter::getImm8_sh8OpValue(
const MCInst &
MI,
unsigned OpNo,
289 int32_t Res = MO.
getImm();
291 assert(((Res >= -32768) && (Res <= 32512) && ((Res & 0xff) == 0)) &&
292 "Unexpected operand value!");
294 return (Res & 0xffff);
298XtensaMCCodeEmitter::getImm12OpValue(
const MCInst &
MI,
unsigned OpNo,
302 int32_t Res = MO.
getImm();
304 assert(((Res >= -2048) && (Res <= 2047)) &&
"Unexpected operand value!");
306 return (Res & 0xfff);
310XtensaMCCodeEmitter::getUimm4OpValue(
const MCInst &
MI,
unsigned OpNo,
316 assert((Res <= 15) &&
"Unexpected operand value!");
322XtensaMCCodeEmitter::getUimm5OpValue(
const MCInst &
MI,
unsigned OpNo,
328 assert((Res <= 31) &&
"Unexpected operand value!");
334XtensaMCCodeEmitter::getShimm1_31OpValue(
const MCInst &
MI,
unsigned OpNo,
340 assert(((Res >= 1) && (Res <= 31)) &&
"Unexpected operand value!");
342 return ((32 - Res) & 0x1f);
346XtensaMCCodeEmitter::getImm1_16OpValue(
const MCInst &
MI,
unsigned OpNo,
352 assert(((Res >= 1) && (Res <= 16)) &&
"Unexpected operand value!");
358XtensaMCCodeEmitter::getB4constOpValue(
const MCInst &
MI,
unsigned OpNo,
406XtensaMCCodeEmitter::getB4constuOpValue(
const MCInst &
MI,
unsigned OpNo,
454#include "XtensaGenMCCodeEmitter.inc"
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
Generic base class for all target subtargets.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCCodeEmitter * createXtensaMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)