LLVM 20.0.0git
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#include "Target/AMDGPU/Disassembler/AMDGPUDisassembler.h"
Public Types | |
enum | OpWidthTy { OPW32 , OPW64 , OPW96 , OPW128 , OPW160 , OPW256 , OPW288 , OPW320 , OPW352 , OPW384 , OPW512 , OPW1024 , OPW16 , OPWV216 , OPWV232 , OPW_LAST_ , OPW_FIRST_ = OPW32 } |
Public Types inherited from llvm::MCDisassembler | |
enum | DecodeStatus { Fail = 0 , SoftFail = 1 , Success = 3 } |
Ternary decode status. More... | |
Static Public Member Functions | |
static MCOperand | decodeIntImmed (unsigned Imm) |
static MCOperand | decodeFPImmed (unsigned ImmWidth, unsigned Imm, AMDGPU::OperandSemantics Sema) |
Additional Inherited Members | |
Public Attributes inherited from llvm::MCDisassembler | |
raw_ostream * | CommentStream = nullptr |
Protected Attributes inherited from llvm::MCDisassembler | |
const MCSubtargetInfo & | STI |
std::unique_ptr< MCSymbolizer > | Symbolizer |
Definition at line 93 of file AMDGPUDisassembler.h.
Enumerator | |
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OPW32 | |
OPW64 | |
OPW96 | |
OPW128 | |
OPW160 | |
OPW256 | |
OPW288 | |
OPW320 | |
OPW352 | |
OPW384 | |
OPW512 | |
OPW1024 | |
OPW16 | |
OPWV216 | |
OPWV232 | |
OPW_LAST_ | |
OPW_FIRST_ |
Definition at line 215 of file AMDGPUDisassembler.h.
AMDGPUDisassembler::AMDGPUDisassembler | ( | const MCSubtargetInfo & | STI, |
MCContext & | Ctx, | ||
MCInstrInfo const * | MCII | ||
) |
Definition at line 63 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::UCVersion::getGFXVersions(), llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm::report_fatal_error(), and llvm::MCDisassembler::STI.
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void AMDGPUDisassembler::convertDPP8Inst | ( | MCInst & | MI | ) | const |
Definition at line 895 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), and MI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertEXPInst | ( | MCInst & | MI | ) | const |
Definition at line 751 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCSubtargetInfo::hasFeature(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertFMAanyK | ( | MCInst & | MI, |
int | ImmLitIdx | ||
) | const |
Definition at line 1141 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), I, insertNamedMCOperand(), llvm::AMDGPU::EncValues::LITERAL_CONST, MI, llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED, and llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED.
Referenced by getInstruction().
void AMDGPUDisassembler::convertMacDPPInst | ( | MCInst & | MI | ) | const |
Definition at line 888 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), insertNamedMCOperand(), and MI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertMIMGInst | ( | MCInst & | MI | ) | const |
Definition at line 945 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::MIMGBaseOpcodeInfo::A16, addOperand(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::SIInstrFlags::Gather4, llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getMIMGOpcode(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterInfo::getSubReg(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasPackedD16(), Info, isGFX10Plus(), MI, llvm::SIInstrFlags::MIMG, llvm::popcount(), llvm::MCDisassembler::STI, and llvm::SIInstrFlags::VSAMPLE.
Referenced by getInstruction().
void AMDGPUDisassembler::convertSDWAInst | ( | MCInst & | MI | ) | const |
Definition at line 775 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), createRegOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertTrue16OpSel | ( | MCInst & | MI | ) | const |
Definition at line 833 of file AMDGPUDisassembler.cpp.
References llvm::MCRegisterClass::contains(), llvm::SISrcMods::DST_OP_SEL, llvm::MCRegisterInfo::getEncodingValue(), llvm::MCOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterClass::getRegister(), MI, llvm::SISrcMods::OP_SEL_0, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.
Referenced by convertDPP8Inst(), and convertVOP3DPPInst().
void AMDGPUDisassembler::convertVINTERPInst | ( | MCInst & | MI | ) | const |
Definition at line 760 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), insertNamedMCOperand(), and MI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertVOP3DPPInst | ( | MCInst & | MI | ) | const |
Definition at line 924 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), and MI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertVOP3PDPPInst | ( | MCInst & | MI | ) | const |
Definition at line 1094 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), and MI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertVOPCDPPInst | ( | MCInst & | MI | ) | const |
Definition at line 1122 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), and MI.
Referenced by getInstruction().
Definition at line 1175 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createReg(), llvm::AMDGPU::getMCReg(), and llvm::MCDisassembler::STI.
Referenced by convertSDWAInst(), createRegOperand(), createSRegOperand(), createVGPR16Operand(), decodeSDWASrc(), decodeSDWAVopcDst(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSrcOp(), decodeVOPDDstYOp(), and getInstruction().
Definition at line 1180 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), and getRegClassName().
Definition at line 1190 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::CommentStream, createRegOperand(), getRegClassName(), and llvm_unreachable.
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
Definition at line 1239 of file AMDGPUDisassembler.cpp.
References createRegOperand().
Definition at line 1742 of file AMDGPUDisassembler.cpp.
References decodeSrcOp(), llvm::MCSubtargetInfo::hasFeature(), OPW32, OPW64, and llvm::MCDisassembler::STI.
Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1 | ( | uint32_t | FourByteBuffer, |
raw_string_ostream & | KdStream | ||
) | const |
Decode as directives that handle COMPUTE_PGM_RSRC1.
FourByteBuffer | - Bytes holding contents of COMPUTE_PGM_RSRC1. |
KdStream | - Stream to write the disassembled directives to. |
Definition at line 1891 of file AMDGPUDisassembler.cpp.
References CHECK_RESERVED_BITS, CHECK_RESERVED_BITS_DESC, CHECK_RESERVED_BITS_DESC_MSG, CHECK_RESERVED_BITS_MSG, GET_FIELD, llvm::AMDGPU::IsaInfo::getSGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), hasArchitectedFlatScratch(), isGFX10Plus(), isGFX12Plus(), isGFX9Plus(), PRINT_DIRECTIVE, and llvm::MCDisassembler::STI.
Referenced by decodeKernelDescriptorDirective().
Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2 | ( | uint32_t | FourByteBuffer, |
raw_string_ostream & | KdStream | ||
) | const |
Decode as directives that handle COMPUTE_PGM_RSRC2.
FourByteBuffer | - Bytes holding contents of COMPUTE_PGM_RSRC2. |
KdStream | - Stream to write the disassembled directives to. |
Definition at line 1999 of file AMDGPUDisassembler.cpp.
References CHECK_RESERVED_BITS, CHECK_RESERVED_BITS_DESC, hasArchitectedFlatScratch(), and PRINT_DIRECTIVE.
Referenced by decodeKernelDescriptorDirective().
Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3 | ( | uint32_t | FourByteBuffer, |
raw_string_ostream & | KdStream | ||
) | const |
Decode as directives that handle COMPUTE_PGM_RSRC3.
FourByteBuffer | - Bytes holding contents of COMPUTE_PGM_RSRC3. |
KdStream | - Stream to write the disassembled directives to. |
Definition at line 2047 of file AMDGPUDisassembler.cpp.
References CHECK_RESERVED_BITS_DESC_MSG, llvm::createStringError(), GET_FIELD, isGFX10Plus(), isGFX11(), isGFX11Plus(), isGFX12Plus(), isGFX90A(), PRINT_DIRECTIVE, and PRINT_PSEUDO_DIRECTIVE_COMMENT.
Referenced by decodeKernelDescriptorDirective().
Definition at line 1752 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::AMDGPU::DPP::DPP8_FI_0, and llvm::AMDGPU::DPP::DPP8_FI_1.
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Definition at line 1392 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), getInlineImmVal16(), getInlineImmVal32(), getInlineImmVal64(), llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN, and llvm_unreachable.
Referenced by decodeNonVGPRSrcOp(), and decodeSDWASrc().
Definition at line 1277 of file AMDGPUDisassembler.cpp.
References assert(), and llvm::MCOperand::createImm().
Referenced by decodeNonVGPRSrcOp(), and decodeSDWASrc().
Expected< bool > AMDGPUDisassembler::decodeKernelDescriptor | ( | StringRef | KdName, |
ArrayRef< uint8_t > | Bytes, | ||
uint64_t | KdAddress | ||
) | const |
Definition at line 2312 of file AMDGPUDisassembler.cpp.
References AMDHSA_BITS_GET, llvm::CallingConv::C, llvm::cantFail(), llvm::createStringError(), decodeKernelDescriptorDirective(), isGFX10Plus(), llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm::little, llvm::outs(), llvm::support::endian::read16(), llvm::ArrayRef< T >::size(), and llvm::raw_string_ostream::str().
Referenced by onSymbolStart().
Expected< bool > AMDGPUDisassembler::decodeKernelDescriptorDirective | ( | DataExtractor::Cursor & | Cursor, |
ArrayRef< uint8_t > | Bytes, | ||
raw_string_ostream & | KdStream | ||
) | const |
Definition at line 2160 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::AMDHSA_COV5, assert(), llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET, createReservedKDBitsError(), createReservedKDBytesError(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), decodeCOMPUTE_PGM_RSRC3(), llvm::DataExtractor::getBytes(), llvm::DataExtractor::getU16(), llvm::DataExtractor::getU32(), llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET, hasArchitectedFlatScratch(), I, isGFX10Plus(), isGFX9(), llvm::amdhsa::KERNARG_PRELOAD_OFFSET, llvm::amdhsa::KERNARG_SIZE_OFFSET, llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm_unreachable, PRINT_DIRECTIVE, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET, llvm::amdhsa::RESERVED0_OFFSET, llvm::amdhsa::RESERVED1_OFFSET, llvm::amdhsa::RESERVED3_OFFSET, llvm::ArrayRef< T >::size(), llvm::DataExtractor::skip(), and llvm::DataExtractor::Cursor::tell().
Referenced by decodeKernelDescriptor().
Definition at line 1260 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), errOperand(), and llvm::ArrayRef< T >::size().
Referenced by decodeNonVGPRSrcOp().
Definition at line 1247 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), errOperand(), llvm::AMDGPU::hasVOPD(), and llvm::MCDisassembler::STI.
MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp | ( | const OpWidthTy | Width, |
unsigned | Val, | ||
bool | MandatoryLiteral = false , |
||
unsigned | ImmWidth = 0 , |
||
AMDGPU::OperandSemantics | Sema = AMDGPU::OperandSemantics::INT |
||
) | const |
Definition at line 1540 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeLiteralConstant(), decodeSpecialReg32(), decodeSpecialReg64(), llvm::AMDGPU::FP64, getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm_unreachable, OPW16, OPW32, OPW64, OPWV216, OPWV232, and SGPR_MAX.
Referenced by decodeSrcOp().
MCOperand AMDGPUDisassembler::decodeSDWASrc | ( | const OpWidthTy | Width, |
unsigned | Val, | ||
unsigned | ImmWidth, | ||
AMDGPU::OperandSemantics | Sema | ||
) | const |
Definition at line 1667 of file AMDGPUDisassembler.cpp.
References createRegOperand(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeSpecialReg32(), getSgprClassId(), getTtmpClassId(), getVgprClassId(), llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm_unreachable, and llvm::MCDisassembler::STI.
Referenced by decodeSDWASrc16(), and decodeSDWASrc32().
Definition at line 1709 of file AMDGPUDisassembler.cpp.
References decodeSDWASrc(), llvm::AMDGPU::FP16, and OPW16.
Definition at line 1713 of file AMDGPUDisassembler.cpp.
References decodeSDWASrc(), llvm::AMDGPU::FP32, and OPW32.
Definition at line 1717 of file AMDGPUDisassembler.cpp.
References assert(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm::MCSubtargetInfo::hasFeature(), OPW32, OPW64, SGPR_MAX, and llvm::MCDisassembler::STI.
Definition at line 1599 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), isGFX11Plus(), and llvm::M0().
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
Definition at line 1635 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), and isGFX11Plus().
Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().
Definition at line 1748 of file AMDGPUDisassembler.cpp.
References decodeSrcOp(), and OPW32.
MCOperand AMDGPUDisassembler::decodeSrcOp | ( | const OpWidthTy | Width, |
unsigned | Val, | ||
bool | MandatoryLiteral = false , |
||
unsigned | ImmWidth = 0 , |
||
AMDGPU::OperandSemantics | Sema = AMDGPU::OperandSemantics::INT |
||
) | const |
Definition at line 1520 of file AMDGPUDisassembler.cpp.
References assert(), createRegOperand(), decodeNonVGPRSrcOp(), getAgprClassId(), and getVgprClassId().
Referenced by decodeBoolReg(), and decodeSplitBarrier().
Definition at line 1758 of file AMDGPUDisassembler.cpp.
References llvm::MCSymbolRefExpr::create(), llvm::MCConstantExpr::create(), llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::MCBinaryExpr::createOr(), llvm::find_if(), llvm::MCDisassembler::getContext(), llvm::AMDGPU::UCVersion::getGFXVersions(), I, and llvm::Version.
Definition at line 1587 of file AMDGPUDisassembler.cpp.
References assert(), createRegOperand(), llvm::MCRegisterInfo::getEncodingValue(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), getVgprClassId(), llvm::MCOperand::isReg(), and OPW32.
Definition at line 1165 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::CommentStream.
Referenced by createRegOperand(), decodeLiteralConstant(), decodeMandatoryLiteralConstant(), decodeSpecialReg32(), and decodeSpecialReg64().
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Returns the disassembly of a single instruction.
Instr | - An MCInst to populate with the contents of the instruction. |
Size | - A value to populate with the size of the instruction, or the number of bytes consumed while attempting to decode an invalid instruction. |
Address | - The address, in the memory space of region, of the first byte of the instruction. |
Bytes | - A reference to the actual bytes of the instruction. |
CStream | - The stream to print comments and annotations on. |
Implements llvm::MCDisassembler.
Definition at line 480 of file AMDGPUDisassembler.cpp.
References llvm::Address, convertDPP8Inst(), convertEXPInst(), convertFMAanyK(), convertMacDPPInst(), convertMIMGInst(), convertSDWAInst(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOP3PDPPInst(), convertVOPCDPPInst(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), createRegOperand(), llvm::SIInstrFlags::DPP, llvm::SIInstrFlags::DS, eat12Bytes(), llvm::SIInstrFlags::EXP, llvm::MCDisassembler::Fail, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::CPol::GLC, llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasGDS(), insertNamedMCOperand(), llvm::SIInstrFlags::IsAtomicRet, isGFX10(), isGFX11(), isGFX11Plus(), isGFX12(), isGFX9(), llvm::AMDGPU::isMAC(), isMacDPP(), isVI(), llvm::AMDGPU::isVOPC64DPP(), MI, llvm::SIInstrFlags::MIMG, llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, llvm::SIInstrFlags::SDWA, llvm::ArrayRef< T >::size(), Size, llvm::ArrayRef< T >::slice(), llvm::SIInstrFlags::SMRD, llvm::SIInstrFlags::SOPK, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, llvm::MCOI::TIED_TO, tryDecodeInst(), llvm::SIInstrFlags::VIMAGE, llvm::SIInstrFlags::VINTERP, llvm::SIInstrFlags::VOP3, llvm::SIInstrFlags::VOP3P, llvm::SIInstrFlags::VOPC, and llvm::SIInstrFlags::VSAMPLE.
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Definition at line 276 of file AMDGPUDisassembler.h.
References llvm::MCInstrInfo::get().
Definition at line 1159 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::getContext(), getRegClassName(), and llvm::MCContext::getRegisterInfo().
Referenced by createRegOperand(), createSRegOperand(), and getRegClassName().
Definition at line 1465 of file AMDGPUDisassembler.cpp.
References assert(), OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
Definition at line 1489 of file AMDGPUDisassembler.cpp.
References assert(), OPW128, OPW16, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
int AMDGPUDisassembler::getTTmpIdx | ( | unsigned | Val | ) | const |
Definition at line 1511 of file AMDGPUDisassembler.cpp.
References isGFX9Plus().
Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().
Definition at line 1414 of file AMDGPUDisassembler.cpp.
References assert(), OPW1024, OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.
Referenced by decodeSDWASrc(), decodeSrcOp(), and decodeVOPDDstYOp().
bool AMDGPUDisassembler::hasArchitectedFlatScratch | ( | ) | const |
Definition at line 1827 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), and decodeKernelDescriptorDirective().
bool AMDGPUDisassembler::hasKernargPreload | ( | ) | const |
Definition at line 1831 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::hasKernargPreload(), and llvm::MCDisassembler::STI.
bool AMDGPUDisassembler::isGFX10 | ( | ) | const |
Definition at line 1805 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX10(), and llvm::MCDisassembler::STI.
Referenced by getInstruction().
bool AMDGPUDisassembler::isGFX10Plus | ( | ) | const |
Definition at line 1807 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX10Plus(), and llvm::MCDisassembler::STI.
Referenced by AMDGPUDisassembler(), convertMIMGInst(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), decodeKernelDescriptor(), decodeKernelDescriptorDirective(), and decodeSDWASrc().
bool AMDGPUDisassembler::isGFX11 | ( | ) | const |
Definition at line 1811 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC3(), and getInstruction().
bool AMDGPUDisassembler::isGFX11Plus | ( | ) | const |
Definition at line 1815 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX11Plus(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC3(), decodeSpecialReg32(), decodeSpecialReg64(), and getInstruction().
bool AMDGPUDisassembler::isGFX12 | ( | ) | const |
Definition at line 1819 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.
Referenced by getInstruction().
bool AMDGPUDisassembler::isGFX12Plus | ( | ) | const |
Definition at line 1823 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX12Plus(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC1(), and decodeCOMPUTE_PGM_RSRC3().
bool AMDGPUDisassembler::isGFX9 | ( | ) | const |
Definition at line 1797 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX9(), and llvm::MCDisassembler::STI.
Referenced by decodeKernelDescriptorDirective(), and getInstruction().
bool AMDGPUDisassembler::isGFX90A | ( | ) | const |
Definition at line 1799 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC3().
bool AMDGPUDisassembler::isGFX9Plus | ( | ) | const |
Definition at line 1803 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX9Plus(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC1(), and getTTmpIdx().
Definition at line 868 of file AMDGPUDisassembler.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::hasNamedOperand(), MI, and llvm::MCOI::TIED_TO.
Referenced by getInstruction().
bool AMDGPUDisassembler::isVI | ( | ) | const |
Definition at line 1793 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.
Referenced by getInstruction().
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overridevirtual |
Used to perform separate target specific disassembly for a particular symbol.
May parse any prelude that precedes instructions after the start of a symbol, or the entire symbol. This is used for example by WebAssembly to decode preludes.
Base implementation returns false. So all targets by default decline to treat symbols separately.
Symbol | - The symbol. |
Size | - The number of bytes consumed. |
Address | - The address, in the memory space of region, of the first byte of the symbol. |
Bytes | - A reference to the actual bytes at the symbol location. |
Reimplemented from llvm::MCDisassembler.
Definition at line 2352 of file AMDGPUDisassembler.cpp.
References llvm::Address, llvm::createStringError(), decodeKernelDescriptor(), Name, Size, llvm::ELF::STT_AMDGPU_HSA_KERNEL, and llvm::ELF::STT_OBJECT.
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overridevirtual |
ELF-specific, set the ABI version from the object header.
Reimplemented from llvm::MCDisassembler.
Definition at line 81 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::getAMDHSACodeObjectVersion(), and llvm::Version.
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inline |
Definition at line 132 of file AMDGPUDisassembler.h.
References llvm::Address, assert(), llvm::MCDisassembler::CommentStream, llvm::MCDisassembler::Fail, MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.
Referenced by getInstruction(), and tryDecodeInst().
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Definition at line 159 of file AMDGPUDisassembler.h.
References llvm::Address, llvm::MCDisassembler::Fail, MI, and tryDecodeInst().