LLVM 22.0.0git
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#include "Target/AMDGPU/Disassembler/AMDGPUDisassembler.h"
Static Public Member Functions | |
static MCOperand | decodeIntImmed (unsigned Imm) |
Additional Inherited Members | |
Public Types inherited from llvm::MCDisassembler | |
enum | DecodeStatus { Fail = 0 , SoftFail = 1 , Success = 3 } |
Ternary decode status. More... | |
Public Attributes inherited from llvm::MCDisassembler | |
raw_ostream * | CommentStream = nullptr |
Protected Attributes inherited from llvm::MCDisassembler | |
const MCSubtargetInfo & | STI |
std::unique_ptr< MCSymbolizer > | Symbolizer |
Definition at line 39 of file AMDGPUDisassembler.h.
AMDGPUDisassembler::AMDGPUDisassembler | ( | const MCSubtargetInfo & | STI, |
MCContext & | Ctx, | ||
MCInstrInfo const * | MCII ) |
Definition at line 57 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::UCVersion::getGFXVersions(), isGFX10Plus(), llvm::MCDisassembler::MCDisassembler(), llvm::reportFatalUsageError(), and llvm::MCDisassembler::STI.
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overridedefault |
References llvm::Address, MI, Size, and llvm::Version.
void AMDGPUDisassembler::convertDPP8Inst | ( | MCInst & | MI | ) | const |
Definition at line 1153 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.
Referenced by getInstruction().
void AMDGPUDisassembler::convertEXPInst | ( | MCInst & | MI | ) | const |
Definition at line 906 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertFMAanyK | ( | MCInst & | MI | ) | const |
Definition at line 1439 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), insertNamedMCOperand(), and MI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertMacDPPInst | ( | MCInst & | MI | ) | const |
Definition at line 1146 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), insertNamedMCOperand(), and MI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertMAIInst | ( | MCInst & | MI | ) | const |
f8f6f4 instructions have different pseudos depending on the used formats.
In the disassembler table, we only have the variants with the largest register classes which assume using an fp8/bf8 format for both operands. The actual register class depends on the format in blgp and cbsz operands. Adjust the register classes depending on the used format.
Definition at line 994 of file AMDGPUDisassembler.cpp.
References adjustMFMA_F8F6F4OpRegClass(), llvm::AMDGPU::getMFMA_F8F6F4_WithFormatArgs(), MI, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcA, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcB, and llvm::AMDGPU::MFMA_F8F6F4_Info::Opcode.
Referenced by getInstruction().
void AMDGPUDisassembler::convertMIMGInst | ( | MCInst & | MI | ) | const |
Definition at line 1223 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::MIMGBaseOpcodeInfo::A16, addOperand(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, CheckVGPROverflow(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::SIInstrFlags::Gather4, llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getMIMGOpcode(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasPackedD16(), isGFX10Plus(), MI, llvm::SIInstrFlags::MIMG, llvm::popcount(), llvm::MCDisassembler::STI, and llvm::SIInstrFlags::VSAMPLE.
Referenced by getInstruction().
void AMDGPUDisassembler::convertSDWAInst | ( | MCInst & | MI | ) | const |
Definition at line 939 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), createRegOperand(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertTrue16OpSel | ( | MCInst & | MI | ) | const |
Definition at line 1091 of file AMDGPUDisassembler.cpp.
References llvm::MCRegisterClass::contains(), llvm::SISrcMods::DST_OP_SEL, llvm::MCOperand::getImm(), llvm::MCRegisterClass::getRegister(), MI, llvm::SISrcMods::OP_SEL_0, Opc, OpIdx, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.
Referenced by convertDPP8Inst(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOPC64DPPInst(), and getInstruction().
void AMDGPUDisassembler::convertVINTERPInst | ( | MCInst & | MI | ) | const |
Definition at line 915 of file AMDGPUDisassembler.cpp.
References convertTrue16OpSel(), llvm::MCOperand::createImm(), insertNamedMCOperand(), and MI.
Referenced by getInstruction().
void AMDGPUDisassembler::convertVOP3DPPInst | ( | MCInst & | MI | ) | const |
Definition at line 1182 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.
Referenced by getInstruction().
void AMDGPUDisassembler::convertVOP3PDPPInst | ( | MCInst & | MI | ) | const |
Definition at line 1378 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.
Referenced by getInstruction().
void AMDGPUDisassembler::convertVOPC64DPPInst | ( | MCInst & | MI | ) | const |
Definition at line 1425 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, Opc, and VOPModifiers::OpSel.
Referenced by getInstruction().
void AMDGPUDisassembler::convertVOPCDPPInst | ( | MCInst & | MI | ) | const |
Definition at line 1406 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.
Referenced by getInstruction().
void AMDGPUDisassembler::convertWMMAInst | ( | MCInst & | MI | ) | const |
Definition at line 1023 of file AMDGPUDisassembler.cpp.
References adjustMFMA_F8F6F4OpRegClass(), llvm::AMDGPU::getWMMA_F8F6F4_WithFormatArgs(), MI, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcA, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcB, and llvm::AMDGPU::MFMA_F8F6F4_Info::Opcode.
Referenced by getInstruction().
Definition at line 1460 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createReg(), llvm::AMDGPU::getMCReg(), and llvm::MCDisassembler::STI.
Referenced by convertSDWAInst(), createRegOperand(), createSRegOperand(), createVGPR16Operand(), decodeSDWASrc(), decodeSDWAVopcDst(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), decodeSrcOp(), decodeVOPDDstYOp(), and getInstruction().
Definition at line 1465 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), and getRegClassName().
Definition at line 1475 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::CommentStream, createRegOperand(), getRegClassName(), and llvm_unreachable.
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
Definition at line 1524 of file AMDGPUDisassembler.cpp.
References createRegOperand().
Definition at line 2108 of file AMDGPUDisassembler.cpp.
References decodeSrcOp(), and llvm::MCDisassembler::STI.
Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1 | ( | uint32_t | FourByteBuffer, |
raw_string_ostream & | KdStream ) const |
Decode as directives that handle COMPUTE_PGM_RSRC1.
FourByteBuffer | - Bytes holding contents of COMPUTE_PGM_RSRC1. |
KdStream | - Stream to write the disassembled directives to. |
Definition at line 2261 of file AMDGPUDisassembler.cpp.
References assert(), CHECK_RESERVED_BITS, CHECK_RESERVED_BITS_DESC, CHECK_RESERVED_BITS_DESC_MSG, CHECK_RESERVED_BITS_MSG, GET_FIELD, llvm::AMDGPU::IsaInfo::getSGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), hasArchitectedFlatScratch(), isGFX10Plus(), isGFX1250(), isGFX12Plus(), isGFX9Plus(), PRINT_DIRECTIVE, PRINT_PSEUDO_DIRECTIVE_COMMENT, and llvm::MCDisassembler::STI.
Referenced by decodeKernelDescriptorDirective().
Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2 | ( | uint32_t | FourByteBuffer, |
raw_string_ostream & | KdStream ) const |
Decode as directives that handle COMPUTE_PGM_RSRC2.
FourByteBuffer | - Bytes holding contents of COMPUTE_PGM_RSRC2. |
KdStream | - Stream to write the disassembled directives to. |
Definition at line 2386 of file AMDGPUDisassembler.cpp.
References CHECK_RESERVED_BITS, CHECK_RESERVED_BITS_DESC, hasArchitectedFlatScratch(), and PRINT_DIRECTIVE.
Referenced by decodeKernelDescriptorDirective().
Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3 | ( | uint32_t | FourByteBuffer, |
raw_string_ostream & | KdStream ) const |
Decode as directives that handle COMPUTE_PGM_RSRC3.
FourByteBuffer | - Bytes holding contents of COMPUTE_PGM_RSRC3. |
KdStream | - Stream to write the disassembled directives to. |
Definition at line 2434 of file AMDGPUDisassembler.cpp.
References CHECK_RESERVED_BITS_DESC_MSG, llvm::createStringError(), GET_FIELD, isGFX10Plus(), isGFX11(), isGFX11Plus(), isGFX1250(), isGFX12Plus(), isGFX90A(), PRINT_DIRECTIVE, and PRINT_PSEUDO_DIRECTIVE_COMMENT.
Referenced by decodeKernelDescriptorDirective().
Definition at line 2120 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::AMDGPU::DPP::DPP8_FI_0, and llvm::AMDGPU::DPP::DPP8_FI_1.
Definition at line 1630 of file AMDGPUDisassembler.cpp.
References assert(), and llvm::MCOperand::createImm().
Expected< bool > AMDGPUDisassembler::decodeKernelDescriptor | ( | StringRef | KdName, |
ArrayRef< uint8_t > | Bytes, | ||
uint64_t | KdAddress ) const |
Definition at line 2716 of file AMDGPUDisassembler.cpp.
References AMDHSA_BITS_GET, llvm::CallingConv::C, llvm::cantFail(), llvm::createStringError(), decodeKernelDescriptorDirective(), isGFX10Plus(), llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm::little, llvm::outs(), llvm::support::endian::read16(), and llvm::raw_string_ostream::str().
Referenced by onSymbolStart().
Expected< bool > AMDGPUDisassembler::decodeKernelDescriptorDirective | ( | DataExtractor::Cursor & | Cursor, |
ArrayRef< uint8_t > | Bytes, | ||
raw_string_ostream & | KdStream ) const |
Definition at line 2564 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::AMDHSA_COV5, assert(), llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET, createReservedKDBitsError(), createReservedKDBytesError(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), decodeCOMPUTE_PGM_RSRC3(), llvm::DataExtractor::getBytes(), llvm::DataExtractor::getU16(), llvm::DataExtractor::getU32(), llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET, hasArchitectedFlatScratch(), I, isGFX10Plus(), isGFX9(), llvm::amdhsa::KERNARG_PRELOAD_OFFSET, llvm::amdhsa::KERNARG_SIZE_OFFSET, llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm_unreachable, PRINT_DIRECTIVE, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET, llvm::amdhsa::RESERVED0_OFFSET, llvm::amdhsa::RESERVED1_OFFSET, llvm::amdhsa::RESERVED3_OFFSET, and llvm::DataExtractor::skip().
Referenced by decodeKernelDescriptor().
Definition at line 1600 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::AMDGPUMCExpr::createLit(), eatBytes(), errOperand(), llvm::MCDisassembler::getContext(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), llvm::Hi_32(), llvm::Lit64, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::MCOperandInfo::OperandType, and llvm::MCDisassembler::STI.
Referenced by decodeNonVGPRSrcOp().
MCOperand AMDGPUDisassembler::decodeLiteralConstant | ( | const MCInstrDesc & | Desc, |
const MCOperandInfo & | OpDesc, | ||
bool | ExtendFP64 ) const |
Definition at line 1560 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::AMDGPUMCExpr::createLit(), eatBytes(), errOperand(), llvm::MCDisassembler::getContext(), llvm::Hi_32(), llvm::Lit64, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::MCOperandInfo::OperandType, llvm::MCDisassembler::STI, llvm::SIInstrFlags::VOP3, and llvm::SIInstrFlags::VOP3P.
Definition at line 1546 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::AMDGPUMCExpr::createLit(), errOperand(), llvm::MCDisassembler::getContext(), llvm::Hi_32(), and llvm::Lit64.
Definition at line 1532 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), errOperand(), llvm::AMDGPU::hasVOPD(), and llvm::MCDisassembler::STI.
MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp | ( | const MCInst & | Inst, |
unsigned | Width, | ||
unsigned | Val ) const |
Definition at line 1891 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), createSRegOperand(), decodeLiteral64Constant(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm_unreachable, SGPR_MAX, and llvm::MCDisassembler::STI.
Referenced by decodeSrcOp().
Definition at line 2036 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), getSgprClassId(), getTtmpClassId(), getVgprClassId(), isGFX10Plus(), llvm_unreachable, and llvm::MCDisassembler::STI.
Referenced by decodeSDWASrc16(), and decodeSDWASrc32().
Definition at line 2075 of file AMDGPUDisassembler.cpp.
References decodeSDWASrc().
Definition at line 2079 of file AMDGPUDisassembler.cpp.
References decodeSDWASrc().
Definition at line 2083 of file AMDGPUDisassembler.cpp.
References assert(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), SGPR_MAX, and llvm::MCDisassembler::STI.
Definition at line 1948 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), isGFX11Plus(), and llvm::M0().
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
Definition at line 1986 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), and isGFX11Plus().
Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().
Definition at line 2018 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), and isGFX11Plus().
Referenced by decodeNonVGPRSrcOp().
Definition at line 2115 of file AMDGPUDisassembler.cpp.
References decodeSrcOp().
MCOperand AMDGPUDisassembler::decodeSrcOp | ( | const MCInst & | Inst, |
unsigned | Width, | ||
unsigned | Val ) const |
Definition at line 1875 of file AMDGPUDisassembler.cpp.
References assert(), createRegOperand(), decodeNonVGPRSrcOp(), getAgprClassId(), and getVgprClassId().
Referenced by decodeBoolReg(), and decodeSplitBarrier().
Definition at line 2126 of file AMDGPUDisassembler.cpp.
References llvm::MCConstantExpr::create(), llvm::MCSymbolRefExpr::create(), llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::MCBinaryExpr::createOr(), llvm::find_if(), llvm::MCDisassembler::getContext(), llvm::AMDGPU::UCVersion::getGFXVersions(), I, and llvm::Version.
Definition at line 1937 of file AMDGPUDisassembler.cpp.
References assert(), createRegOperand(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), getVgprClassId(), and llvm::MCOperand::isReg().
Definition at line 1450 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::CommentStream.
Referenced by createRegOperand(), decodeLiteral64Constant(), decodeLiteralConstant(), decodeMandatoryLiteral64Constant(), decodeMandatoryLiteralConstant(), decodeSpecialReg32(), decodeSpecialReg64(), and decodeSpecialReg96Plus().
Definition at line 1775 of file AMDGPUDisassembler.cpp.
References llvm_unreachable.
Referenced by decodeSrcOp().
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overridevirtual |
Returns the disassembly of a single instruction.
Instr | - An MCInst to populate with the contents of the instruction. |
Size | - A value to populate with the size of the instruction, or the number of bytes consumed while attempting to decode an invalid instruction. |
Address | - The address, in the memory space of region, of the first byte of the instruction. |
Bytes | - A reference to the actual bytes of the instruction. |
CStream | - The stream to print comments and annotations on. |
Implements llvm::MCDisassembler.
Definition at line 553 of file AMDGPUDisassembler.cpp.
References llvm::Address, convertDPP8Inst(), convertEXPInst(), convertFMAanyK(), convertMacDPPInst(), convertMAIInst(), convertMIMGInst(), convertSDWAInst(), convertTrue16OpSel(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOP3PDPPInst(), convertVOPC64DPPInst(), convertVOPCDPPInst(), convertWMMAInst(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), createRegOperand(), llvm::SIInstrFlags::DPP, llvm::SIInstrFlags::DS, eat12Bytes(), eat16Bytes(), eatBytes(), llvm::SIInstrFlags::EXP, llvm::MCDisassembler::Fail, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::CPol::GLC, llvm::AMDGPU::hasGDS(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), llvm::SIInstrFlags::IsAtomicRet, isBufferInstruction(), isGFX10(), isGFX11(), isGFX11Plus(), isGFX12(), isGFX1250(), isGFX12Plus(), isGFX9(), llvm::AMDGPU::isMAC(), isMacDPP(), llvm::SIInstrFlags::IsMAI, isVI(), llvm::AMDGPU::isVOPC64DPP(), llvm::SIInstrFlags::IsWMMA, MI, llvm::SIInstrFlags::MIMG, llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, llvm::SIInstrFlags::SDWA, llvm::SignExtend64(), Size, llvm::ArrayRef< T >::size(), llvm::ArrayRef< T >::slice(), llvm::SIInstrFlags::SMRD, llvm::MCDisassembler::SoftFail, llvm::SIInstrFlags::SOPK, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, llvm::MCOI::TIED_TO, tryDecodeInst(), llvm::SIInstrFlags::VIMAGE, llvm::SIInstrFlags::VINTERP, llvm::SIInstrFlags::VOP3, llvm::SIInstrFlags::VOP3P, llvm::SIInstrFlags::VOPC, and llvm::SIInstrFlags::VSAMPLE.
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Definition at line 174 of file AMDGPUDisassembler.h.
References llvm::MCInstrInfo::get().
Definition at line 1444 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::getContext(), getRegClassName(), and llvm::MCContext::getRegisterInfo().
Referenced by createRegOperand(), createSRegOperand(), and getRegClassName().
Definition at line 1808 of file AMDGPUDisassembler.cpp.
References llvm_unreachable.
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
Definition at line 1839 of file AMDGPUDisassembler.cpp.
References llvm_unreachable.
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
int AMDGPUDisassembler::getTTmpIdx | ( | unsigned | Val | ) | const |
Definition at line 1866 of file AMDGPUDisassembler.cpp.
References isGFX9Plus().
Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().
Definition at line 1740 of file AMDGPUDisassembler.cpp.
References llvm_unreachable.
Referenced by decodeSDWASrc(), decodeSrcOp(), and decodeVOPDDstYOp().
bool AMDGPUDisassembler::hasArchitectedFlatScratch | ( | ) | const |
Definition at line 2197 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), and decodeKernelDescriptorDirective().
bool AMDGPUDisassembler::hasKernargPreload | ( | ) | const |
Definition at line 2201 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::hasKernargPreload(), and llvm::MCDisassembler::STI.
Check if the instruction is a buffer operation (MUBUF, MTBUF, or S_BUFFER)
Definition at line 2800 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::getSMEMIsBuffer(), MI, llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, and llvm::SIInstrFlags::SMRD.
Referenced by getInstruction().
bool AMDGPUDisassembler::isGFX10 | ( | ) | const |
Definition at line 2173 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX10(), and llvm::MCDisassembler::STI.
Referenced by getInstruction().
bool AMDGPUDisassembler::isGFX10Plus | ( | ) | const |
Definition at line 2175 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX10Plus(), and llvm::MCDisassembler::STI.
Referenced by AMDGPUDisassembler(), convertMIMGInst(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), decodeKernelDescriptor(), decodeKernelDescriptorDirective(), and decodeSDWASrc().
bool AMDGPUDisassembler::isGFX11 | ( | ) | const |
Definition at line 2179 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC3(), and getInstruction().
bool AMDGPUDisassembler::isGFX11Plus | ( | ) | const |
Definition at line 2183 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX11Plus(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC3(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), and getInstruction().
bool AMDGPUDisassembler::isGFX12 | ( | ) | const |
Definition at line 2187 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::STI.
Referenced by getInstruction().
bool AMDGPUDisassembler::isGFX1250 | ( | ) | const |
Definition at line 2195 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX1250(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), and getInstruction().
bool AMDGPUDisassembler::isGFX12Plus | ( | ) | const |
Definition at line 2191 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX12Plus(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), and getInstruction().
bool AMDGPUDisassembler::isGFX9 | ( | ) | const |
Definition at line 2165 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX9(), and llvm::MCDisassembler::STI.
Referenced by decodeKernelDescriptorDirective(), and getInstruction().
bool AMDGPUDisassembler::isGFX90A | ( | ) | const |
Definition at line 2167 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC3().
bool AMDGPUDisassembler::isGFX9Plus | ( | ) | const |
Definition at line 2171 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX9Plus(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC1(), and getTTmpIdx().
Definition at line 1126 of file AMDGPUDisassembler.cpp.
References assert(), llvm::AMDGPU::hasNamedOperand(), MI, and llvm::MCOI::TIED_TO.
Referenced by getInstruction().
bool AMDGPUDisassembler::isVI | ( | ) | const |
Definition at line 2161 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::STI.
Referenced by getInstruction().
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overridevirtual |
Used to perform separate target specific disassembly for a particular symbol.
May parse any prelude that precedes instructions after the start of a symbol, or the entire symbol. This is used for example by WebAssembly to decode preludes.
Base implementation returns false. So all targets by default decline to treat symbols separately.
Symbol | - The symbol. |
Size | - The number of bytes consumed. |
Address | - The address, in the memory space of region, of the first byte of the symbol. |
Bytes | - A reference to the actual bytes at the symbol location. |
Reimplemented from llvm::MCDisassembler.
Definition at line 2756 of file AMDGPUDisassembler.cpp.
References llvm::Address, llvm::createStringError(), decodeKernelDescriptor(), Size, llvm::ELF::STT_AMDGPU_HSA_KERNEL, and llvm::ELF::STT_OBJECT.
|
overridevirtual |
ELF-specific, set the ABI version from the object header.
Reimplemented from llvm::MCDisassembler.
Definition at line 76 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::getAMDHSACodeObjectVersion(), and llvm::Version.
DecodeStatus AMDGPUDisassembler::tryDecodeInst | ( | const uint8_t * | Table, |
MCInst & | MI, | ||
InsnType | Inst, | ||
uint64_t | Address, | ||
raw_ostream & | Comments ) const |
Definition at line 424 of file AMDGPUDisassembler.cpp.
References llvm::Address, assert(), llvm::MCDisassembler::CommentStream, llvm::MCDisassembler::Fail, MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.
Referenced by getInstruction(), and tryDecodeInst().
DecodeStatus AMDGPUDisassembler::tryDecodeInst | ( | const uint8_t * | Table1, |
const uint8_t * | Table2, | ||
MCInst & | MI, | ||
InsnType | Inst, | ||
uint64_t | Address, | ||
raw_ostream & | Comments ) const |
Definition at line 453 of file AMDGPUDisassembler.cpp.
References llvm::Address, llvm::MCDisassembler::Fail, MI, T, and tryDecodeInst().