LLVM 22.0.0git
AMDGPUDisassembler.h
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1//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This file contains declaration for AMDGPU ISA disassembler
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17
18#include "SIDefines.h"
19#include "llvm/ADT/APInt.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
25#include <memory>
26
27namespace llvm {
28
29class MCAsmInfo;
30class MCInst;
31class MCOperand;
32class MCSubtargetInfo;
33class Twine;
34
35//===----------------------------------------------------------------------===//
36// AMDGPUDisassembler
37//===----------------------------------------------------------------------===//
38
40private:
41 std::unique_ptr<MCInstrInfo const> const MCII;
42 const MCRegisterInfo &MRI;
43 const MCAsmInfo &MAI;
44 const unsigned HwModeRegClass;
45 const unsigned TargetMaxInstBytes;
46 mutable ArrayRef<uint8_t> Bytes;
47 mutable uint32_t Literal;
48 mutable uint64_t Literal64;
49 mutable bool HasLiteral;
50 mutable std::optional<bool> EnableWavefrontSize32;
51 unsigned CodeObjectVersion;
52 const MCExpr *UCVersionW64Expr;
53 const MCExpr *UCVersionW32Expr;
54 const MCExpr *UCVersionMDPExpr;
55
56 const MCExpr *createConstantSymbolExpr(StringRef Id, int64_t Val);
57
58 void decodeImmOperands(MCInst &MI, const MCInstrInfo &MCII) const;
59
60public:
62 MCInstrInfo const *MCII);
63 ~AMDGPUDisassembler() override = default;
64
65 void setABIVersion(unsigned Version) override;
66
69 raw_ostream &CS) const override;
70
71 const char* getRegClassName(unsigned RegClassID) const;
72
73 MCOperand createRegOperand(unsigned int RegId) const;
74 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
75 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
76 MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;
77
78 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
79
80 template <typename InsnType>
81 DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
82 uint64_t Address, raw_ostream &Comments) const;
83 template <typename InsnType>
84 DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2,
85 MCInst &MI, InsnType Inst, uint64_t Address,
86 raw_ostream &Comments) const;
87
90 uint64_t Address) const override;
91
94 uint64_t KdAddress) const;
95
99 raw_string_ostream &KdStream) const;
100
101 /// Decode as directives that handle COMPUTE_PGM_RSRC1.
102 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
103 /// \param KdStream - Stream to write the disassembled directives to.
104 // NOLINTNEXTLINE(readability-identifier-naming)
106 raw_string_ostream &KdStream) const;
107
108 /// Decode as directives that handle COMPUTE_PGM_RSRC2.
109 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
110 /// \param KdStream - Stream to write the disassembled directives to.
111 // NOLINTNEXTLINE(readability-identifier-naming)
113 raw_string_ostream &KdStream) const;
114
115 /// Decode as directives that handle COMPUTE_PGM_RSRC3.
116 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC3.
117 /// \param KdStream - Stream to write the disassembled directives to.
118 // NOLINTNEXTLINE(readability-identifier-naming)
120 raw_string_ostream &KdStream) const;
121
122 void convertEXPInst(MCInst &MI) const;
123 void convertVINTERPInst(MCInst &MI) const;
124 void convertFMAanyK(MCInst &MI) const;
125 void convertSDWAInst(MCInst &MI) const;
126 void convertMAIInst(MCInst &MI) const;
127 void convertWMMAInst(MCInst &MI) const;
128 void convertDPP8Inst(MCInst &MI) const;
129 void convertMIMGInst(MCInst &MI) const;
130 void convertVOP3DPPInst(MCInst &MI) const;
131 void convertVOP3PDPPInst(MCInst &MI) const;
132 void convertVOPCDPPInst(MCInst &MI) const;
133 void convertVOPC64DPPInst(MCInst &MI) const;
134 void convertMacDPPInst(MCInst &MI) const;
135 void convertTrue16OpSel(MCInst &MI) const;
136
137 unsigned getVgprClassId(unsigned Width) const;
138 unsigned getAgprClassId(unsigned Width) const;
139 unsigned getSgprClassId(unsigned Width) const;
140 unsigned getTtmpClassId(unsigned Width) const;
141
142 static MCOperand decodeIntImmed(unsigned Imm);
143
144 MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
147 const MCOperandInfo &OpDesc,
148 bool ExtendFP64) const;
149 MCOperand decodeLiteral64Constant(const MCInst &Inst) const;
150
151 MCOperand decodeSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const;
152
153 MCOperand decodeNonVGPRSrcOp(const MCInst &Inst, unsigned Width,
154 unsigned Val) const;
155
156 MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
157 MCOperand decodeSpecialReg32(unsigned Val) const;
158 MCOperand decodeSpecialReg64(unsigned Val) const;
159 MCOperand decodeSpecialReg96Plus(unsigned Val) const;
160
161 MCOperand decodeSDWASrc(unsigned Width, unsigned Val) const;
162 MCOperand decodeSDWASrc16(unsigned Val) const;
163 MCOperand decodeSDWASrc32(unsigned Val) const;
164 MCOperand decodeSDWAVopcDst(unsigned Val) const;
165
166 MCOperand decodeBoolReg(const MCInst &Inst, unsigned Val) const;
167 MCOperand decodeSplitBarrier(const MCInst &Inst, unsigned Val) const;
168 MCOperand decodeDpp8FI(unsigned Val) const;
169
170 MCOperand decodeVersionImm(unsigned Imm) const;
171
172 int getTTmpIdx(unsigned Val) const;
173
174 const MCInstrInfo *getMCII() const { return MCII.get(); }
175
176 bool isVI() const;
177 bool isGFX9() const;
178 bool isGFX90A() const;
179 bool isGFX9Plus() const;
180 bool isGFX10() const;
181 bool isGFX10Plus() const;
182 bool isGFX11() const;
183 bool isGFX11Plus() const;
184 bool isGFX12() const;
185 bool isGFX12Plus() const;
186 bool isGFX1250() const;
187
188 bool hasArchitectedFlatScratch() const;
189 bool hasKernargPreload() const;
190
191 bool isMacDPP(MCInst &MI) const;
192
193 /// Check if the instruction is a buffer operation (MUBUF, MTBUF, or S_BUFFER)
194 bool isBufferInstruction(const MCInst &MI) const;
195};
196
197//===----------------------------------------------------------------------===//
198// AMDGPUSymbolizer
199//===----------------------------------------------------------------------===//
200
202private:
203 void *DisInfo;
204 std::vector<uint64_t> ReferencedAddresses;
205
206public:
207 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
208 void *disInfo)
209 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
210
211 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
212 int64_t Value, uint64_t Address, bool IsBranch,
213 uint64_t Offset, uint64_t OpSize,
214 uint64_t InstSize) override;
215
217 int64_t Value,
218 uint64_t Address) override;
219
221 return ReferencedAddresses;
222 }
223};
224
225} // end namespace llvm
226
227#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
This file implements a class to represent arbitrary precision integral constant values and operations...
IRTranslator LLVM IR MI
This file defines the SmallString class.
const MCInstrInfo * getMCII() const
MCOperand decodeNonVGPRSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const
void convertVOPC64DPPInst(MCInst &MI) const
bool isBufferInstruction(const MCInst &MI) const
Check if the instruction is a buffer operation (MUBUF, MTBUF, or S_BUFFER)
void convertEXPInst(MCInst &MI) const
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
Expected< bool > decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
MCOperand decodeSplitBarrier(const MCInst &Inst, unsigned Val) const
Expected< bool > decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
void convertVOPCDPPInst(MCInst &MI) const
MCOperand decodeLiteral64Constant(const MCInst &Inst) const
MCOperand decodeLiteralConstant(const MCInstrDesc &Desc, const MCOperandInfo &OpDesc, bool ExtendFP64) const
MCOperand decodeSpecialReg96Plus(unsigned Val) const
MCOperand decodeSDWASrc32(unsigned Val) const
void setABIVersion(unsigned Version) override
ELF-specific, set the ABI version from the object header.
Expected< bool > decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
unsigned getAgprClassId(unsigned Width) const
MCOperand decodeDpp8FI(unsigned Val) const
MCOperand decodeSDWASrc(unsigned Width, unsigned Val) const
void convertFMAanyK(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
void convertDPP8Inst(MCInst &MI) const
MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
MCOperand decodeVersionImm(unsigned Imm) const
Expected< bool > decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
void convertVOP3DPPInst(MCInst &MI) const
void convertTrue16OpSel(MCInst &MI) const
MCOperand decodeSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
Expected< bool > decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC3.
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
~AMDGPUDisassembler() override=default
void convertVINTERPInst(MCInst &MI) const
void convertSDWAInst(MCInst &MI) const
unsigned getSgprClassId(unsigned Width) const
static MCOperand decodeIntImmed(unsigned Imm)
void convertWMMAInst(MCInst &MI) const
MCOperand decodeBoolReg(const MCInst &Inst, unsigned Val) const
unsigned getVgprClassId(unsigned Width) const
void convertMAIInst(MCInst &MI) const
f8f6f4 instructions have different pseudos depending on the used formats.
unsigned getTtmpClassId(unsigned Width) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
MCOperand decodeMandatoryLiteral64Constant(uint64_t Imm) const
void convertMIMGInst(MCInst &MI) const
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
void convertVOP3PDPPInst(MCInst &MI) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
MCOperand decodeSDWASrc16(unsigned Val) const
Expected< bool > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Used to perform separate target specific disassembly for a particular symbol.
ArrayRef< uint64_t > getReferencedAddresses() const override
Get the MCSymbolizer's list of addresses that were referenced by symbolizable operands but not resolv...
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Tagged union holding either a T or a Error.
Definition Error.h:485
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition MCAsmInfo.h:64
Context object for machine code objects.
Definition MCContext.h:83
MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
const MCSubtargetInfo & STI
DecodeStatus
Ternary decode status.
Base class for the full range of assembler expressions which are needed for parsing.
Definition MCExpr.h:34
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition MCInstrInfo.h:90
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition MCInstrDesc.h:87
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
MCSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > RelInfo)
Construct an MCSymbolizer, taking ownership of RelInfo.
std::unique_ptr< MCRelocationInfo > RelInfo
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition Twine.h:82
LLVM Value Representation.
Definition Value.h:75
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
A raw_ostream that writes to an std::string.
This is an optimization pass for GlobalISel generic memory operations.
@ Offset
Definition DWP.cpp:477
Op::Description Desc
FunctionAddr VTableAddr uintptr_t uintptr_t Version
Definition InstrProf.h:302
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1869
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:867