LLVM  16.0.0git
LanaiMCTargetDesc.h
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1 //===-- LanaiMCTargetDesc.h - Lanai Target Descriptions ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Lanai specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_LANAI_MCTARGETDESC_LANAIMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_LANAI_MCTARGETDESC_LANAIMCTARGETDESC_H
15 
16 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/DataTypes.h"
19 
20 namespace llvm {
21 class MCAsmBackend;
22 class MCCodeEmitter;
23 class MCContext;
24 class MCInstrInfo;
25 class MCObjectTargetWriter;
26 class MCSubtargetInfo;
27 class Target;
28 
29 MCCodeEmitter *createLanaiMCCodeEmitter(const MCInstrInfo &MCII,
30  MCContext &Ctx);
31 
32 MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI,
33  const MCRegisterInfo &MRI,
34  const MCTargetOptions &Options);
35 
36 std::unique_ptr<MCObjectTargetWriter> createLanaiELFObjectWriter(uint8_t OSABI);
37 } // namespace llvm
38 
39 // Defines symbolic names for Lanai registers. This defines a mapping from
40 // register name to register number.
41 #define GET_REGINFO_ENUM
42 #include "LanaiGenRegisterInfo.inc"
43 
44 // Defines symbolic names for the Lanai instructions.
45 #define GET_INSTRINFO_ENUM
46 #define GET_INSTRINFO_MC_HELPER_DECLS
47 #include "LanaiGenInstrInfo.inc"
48 
49 #define GET_SUBTARGETINFO_ENUM
50 #include "LanaiGenSubtargetInfo.inc"
51 
52 #endif // LLVM_LIB_TARGET_LANAI_MCTARGETDESC_LANAIMCTARGETDESC_H
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCTargetOptions.h
llvm::createLanaiMCCodeEmitter
MCCodeEmitter * createLanaiMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: LanaiMCCodeEmitter.cpp:306
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:852
T
#define T
Definition: Mips16ISelLowering.cpp:341
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createLanaiAsmBackend
MCAsmBackend * createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: LanaiAsmBackend.cpp:161
MCRegisterInfo.h
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::createLanaiELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createLanaiELFObjectWriter(uint8_t OSABI)
Definition: LanaiELFObjectWriter.cpp:90
DataTypes.h