#include <ARMSubtarget.h>
Public Types | |
| enum | { isELF, isDarwin } |
| enum | { ARM_ABI_APCS, ARM_ABI_AAPCS } |
Public Member Functions | |
| ARMSubtarget (const std::string &TT, const std::string &CPU, const std::string &FS, const TargetOptions &Options) | |
| unsigned | getMaxInlineSizeThreshold () const |
| void | ParseSubtargetFeatures (StringRef CPU, StringRef FS) |
| virtual void | resetSubtargetFeatures (const MachineFunction *MF) |
| Reset the features for the ARM target. | |
| void | computeIssueWidth () |
| bool | hasV4TOps () const |
| bool | hasV5TOps () const |
| bool | hasV5TEOps () const |
| bool | hasV6Ops () const |
| bool | hasV6T2Ops () const |
| bool | hasV7Ops () const |
| bool | isCortexA5 () const |
| bool | isCortexA8 () const |
| bool | isCortexA9 () const |
| bool | isCortexA15 () const |
| bool | isSwift () const |
| bool | isCortexM3 () const |
| bool | isLikeA9 () const |
| bool | isCortexR5 () const |
| bool | hasARMOps () const |
| bool | hasVFP2 () const |
| bool | hasVFP3 () const |
| bool | hasVFP4 () const |
| bool | hasNEON () const |
| bool | useNEONForSinglePrecisionFP () const |
| bool | hasDivide () const |
| bool | hasDivideInARMMode () const |
| bool | hasT2ExtractPack () const |
| bool | hasDataBarrier () const |
| bool | useMulOps () const |
| bool | useFPVMLx () const |
| bool | hasVMLxForwarding () const |
| bool | isFPBrccSlow () const |
| bool | isFPOnlySP () const |
| bool | hasTrustZone () const |
| bool | prefers32BitThumb () const |
| bool | avoidCPSRPartialUpdate () const |
| bool | avoidMOVsShifterOperand () const |
| bool | hasRAS () const |
| bool | hasMPExtension () const |
| bool | hasThumb2DSP () const |
| bool | useNaClTrap () const |
| bool | hasFP16 () const |
| bool | hasD16 () const |
| const Triple & | getTargetTriple () const |
| bool | isTargetIOS () const |
| bool | isTargetDarwin () const |
| bool | isTargetNaCl () const |
| bool | isTargetLinux () const |
| bool | isTargetELF () const |
| bool | isAPCS_ABI () const |
| bool | isAAPCS_ABI () const |
| bool | isThumb () const |
| bool | isThumb1Only () const |
| bool | isThumb2 () const |
| bool | hasThumb2 () const |
| bool | isMClass () const |
| bool | isARClass () const |
| bool | isR9Reserved () const |
| bool | useMovt () const |
| bool | supportsTailCall () const |
| bool | allowsUnalignedMem () const |
| const std::string & | getCPUString () const |
| unsigned | getMispredictionPenalty () const |
| bool | enablePostRAScheduler (CodeGenOpt::Level OptLevel, TargetSubtargetInfo::AntiDepBreakMode &Mode, RegClassVector &CriticalPathRCs) const |
| enablePostRAScheduler - True at 'More' optimization. | |
| const InstrItineraryData & | getInstrItineraryData () const |
| unsigned | getStackAlignment () const |
| bool | GVIsIndirectSymbol (const GlobalValue *GV, Reloc::Model RelocM) const |
Public Attributes | |
| enum llvm::ARMSubtarget:: { ... } | TargetType |
| enum llvm::ARMSubtarget:: { ... } | TargetABI |
Protected Types | |
| enum | ARMProcFamilyEnum { Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift } |
Protected Attributes | |
| ARMProcFamilyEnum | ARMProcFamily |
| ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. | |
| bool | HasV4TOps |
| bool | HasV5TOps |
| bool | HasV5TEOps |
| bool | HasV6Ops |
| bool | HasV6T2Ops |
| bool | HasV7Ops |
| bool | HasVFPv2 |
| bool | HasVFPv3 |
| bool | HasVFPv4 |
| bool | HasNEON |
| bool | UseNEONForSinglePrecisionFP |
| bool | UseMulOps |
| bool | SlowFPVMLx |
| bool | HasVMLxForwarding |
| bool | SlowFPBrcc |
| SlowFPBrcc - True if floating point compare + branch is slow. | |
| bool | InThumbMode |
| InThumbMode - True if compiling for Thumb, false for ARM. | |
| bool | HasThumb2 |
| HasThumb2 - True if Thumb2 instructions are supported. | |
| bool | IsMClass |
| bool | NoARM |
| NoARM - True if subtarget does not support ARM mode execution. | |
| bool | PostRAScheduler |
| PostRAScheduler - True if using post-register-allocation scheduler. | |
| bool | IsR9Reserved |
| IsR9Reserved - True if R9 is a not available as general purpose register. | |
| bool | UseMovt |
| bool | SupportsTailCall |
| bool | HasFP16 |
| bool | HasD16 |
| bool | HasHardwareDivide |
| HasHardwareDivide - True if subtarget supports [su]div. | |
| bool | HasHardwareDivideInARM |
| HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode. | |
| bool | HasT2ExtractPack |
| bool | HasDataBarrier |
| bool | Pref32BitThumb |
| bool | AvoidCPSRPartialUpdate |
| bool | AvoidMOVsShifterOperand |
| bool | HasRAS |
| bool | HasMPExtension |
| bool | FPOnlySP |
| bool | HasTrustZone |
| HasTrustZone - if true, processor supports TrustZone security extensions. | |
| bool | AllowsUnalignedMem |
| bool | Thumb2DSP |
| bool | UseNaClTrap |
| NaCl TRAP instruction is generated instead of the regular TRAP. | |
| bool | UnsafeFPMath |
| Target machine allowed unsafe FP math (such as use of NEON fp) | |
| unsigned | stackAlignment |
| std::string | CPUString |
| CPUString - String name of used CPU. | |
| Triple | TargetTriple |
| TargetTriple - What processor and OS we're targeting. | |
| const MCSchedModel * | SchedModel |
| SchedModel - Processor specific instruction costs. | |
| InstrItineraryData | InstrItins |
| Selected instruction itineraries (one entry per itinerary class.) | |
| const TargetOptions & | Options |
| Options passed via command line that could influence the target. | |
Detailed Description
Definition at line 31 of file ARMSubtarget.h.
Member Enumeration Documentation
| anonymous enum |
Definition at line 189 of file ARMSubtarget.h.
| anonymous enum |
Definition at line 193 of file ARMSubtarget.h.
enum llvm::ARMSubtarget::ARMProcFamilyEnum [protected] |
Definition at line 33 of file ARMSubtarget.h.
Constructor & Destructor Documentation
| ARMSubtarget::ARMSubtarget | ( | const std::string & | TT, |
| const std::string & | CPU, | ||
| const std::string & | FS, | ||
| const TargetOptions & | Options | ||
| ) |
This constructor initializes the data members to match that of the specified triple.
Definition at line 60 of file ARMSubtarget.cpp.
References resetSubtargetFeatures().
Member Function Documentation
| bool llvm::ARMSubtarget::allowsUnalignedMem | ( | ) | const [inline] |
Definition at line 292 of file ARMSubtarget.h.
References AllowsUnalignedMem.
Referenced by llvm::ARMTargetLowering::allowsUnalignedMemoryAccesses().
| bool llvm::ARMSubtarget::avoidCPSRPartialUpdate | ( | ) | const [inline] |
Definition at line 259 of file ARMSubtarget.h.
References AvoidCPSRPartialUpdate.
| bool llvm::ARMSubtarget::avoidMOVsShifterOperand | ( | ) | const [inline] |
Definition at line 260 of file ARMSubtarget.h.
References AvoidMOVsShifterOperand.
| void llvm::ARMSubtarget::computeIssueWidth | ( | ) |
| bool ARMSubtarget::enablePostRAScheduler | ( | CodeGenOpt::Level | OptLevel, |
| TargetSubtargetInfo::AntiDepBreakMode & | Mode, | ||
| RegClassVector & | CriticalPathRCs | ||
| ) | const |
enablePostRAScheduler - True at 'More' optimization.
Definition at line 271 of file ARMSubtarget.cpp.
References llvm::TargetSubtargetInfo::ANTIDEP_CRITICAL, llvm::Reloc::Default, and PostRAScheduler.
| const std::string& llvm::ARMSubtarget::getCPUString | ( | ) | const [inline] |
Definition at line 294 of file ARMSubtarget.h.
References CPUString.
Referenced by llvm::ARMTargetMachine::ARMTargetMachine().
| const InstrItineraryData& llvm::ARMSubtarget::getInstrItineraryData | ( | ) | const [inline] |
getInstrItins - Return the instruction itineraies based on subtarget selection.
Definition at line 305 of file ARMSubtarget.h.
References InstrItins.
| unsigned llvm::ARMSubtarget::getMaxInlineSizeThreshold | ( | ) | const [inline] |
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition at line 206 of file ARMSubtarget.h.
References isThumb1Only().
Referenced by llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy().
| unsigned ARMSubtarget::getMispredictionPenalty | ( | ) | const |
Definition at line 267 of file ARMSubtarget.cpp.
References llvm::MCSchedModel::MispredictPenalty, and SchedModel.
Referenced by llvm::ARMBaseInstrInfo::isProfitableToIfCvt().
| unsigned llvm::ARMSubtarget::getStackAlignment | ( | ) | const [inline] |
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.
Definition at line 310 of file ARMSubtarget.h.
References stackAlignment.
| const Triple& llvm::ARMSubtarget::getTargetTriple | ( | ) | const [inline] |
Definition at line 269 of file ARMSubtarget.h.
References TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
| bool ARMSubtarget::GVIsIndirectSymbol | ( | const GlobalValue * | GV, |
| Reloc::Model | RelocM | ||
| ) | const |
GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
Definition at line 216 of file ARMSubtarget.cpp.
References llvm::GlobalValue::hasAvailableExternallyLinkage(), llvm::GlobalValue::hasCommonLinkage(), llvm::GlobalValue::hasHiddenVisibility(), llvm::GlobalValue::hasLocalLinkage(), llvm::GlobalValue::isDeclaration(), llvm::GlobalValue::isMaterializable(), isTargetDarwin(), llvm::GlobalValue::isWeakForLinker(), llvm::Reloc::PIC_, and llvm::Reloc::Static.
| bool llvm::ARMSubtarget::hasARMOps | ( | ) | const [inline] |
Definition at line 239 of file ARMSubtarget.h.
References NoARM.
Referenced by llvm::ARMTargetMachine::ARMTargetMachine().
| bool llvm::ARMSubtarget::hasD16 | ( | ) | const [inline] |
Definition at line 267 of file ARMSubtarget.h.
References HasD16.
Referenced by llvm::ARMBaseRegisterInfo::getReservedRegs().
| bool llvm::ARMSubtarget::hasDataBarrier | ( | ) | const [inline] |
Definition at line 251 of file ARMSubtarget.h.
References HasDataBarrier.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and LowerATOMIC_FENCE().
| bool llvm::ARMSubtarget::hasDivide | ( | ) | const [inline] |
Definition at line 248 of file ARMSubtarget.h.
References HasHardwareDivide.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
| bool llvm::ARMSubtarget::hasDivideInARMMode | ( | ) | const [inline] |
Definition at line 249 of file ARMSubtarget.h.
References HasHardwareDivideInARM.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
| bool llvm::ARMSubtarget::hasFP16 | ( | ) | const [inline] |
Definition at line 266 of file ARMSubtarget.h.
References HasFP16.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
| bool llvm::ARMSubtarget::hasMPExtension | ( | ) | const [inline] |
Definition at line 262 of file ARMSubtarget.h.
References HasMPExtension.
Referenced by LowerPREFETCH().
| bool llvm::ARMSubtarget::hasNEON | ( | ) | const [inline] |
Definition at line 244 of file ARMSubtarget.h.
References HasNEON.
Referenced by AddCombineToVPADDL(), llvm::ARMTargetLowering::allowsUnalignedMemoryAccesses(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::getOptimalMemOpType(), llvm::ARMTargetLowering::getRegClassFor(), LowerCTPOP(), LowerShift(), PerformExtendCombine(), PerformORCombine(), PerformSELECT_CCCombine(), PerformShiftCombine(), PerformVCVTCombine(), PerformVDIVCombine(), and useNEONForSinglePrecisionFP().
| bool llvm::ARMSubtarget::hasRAS | ( | ) | const [inline] |
Definition at line 261 of file ARMSubtarget.h.
References HasRAS.
| bool llvm::ARMSubtarget::hasT2ExtractPack | ( | ) | const [inline] |
Definition at line 250 of file ARMSubtarget.h.
References HasT2ExtractPack.
Referenced by PerformORCombine().
| bool llvm::ARMSubtarget::hasThumb2 | ( | ) | const [inline] |
Definition at line 283 of file ARMSubtarget.h.
References HasThumb2.
| bool llvm::ARMSubtarget::hasThumb2DSP | ( | ) | const [inline] |
Definition at line 263 of file ARMSubtarget.h.
References Thumb2DSP.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
| bool llvm::ARMSubtarget::hasTrustZone | ( | ) | const [inline] |
Definition at line 257 of file ARMSubtarget.h.
References HasTrustZone.
| bool llvm::ARMSubtarget::hasV4TOps | ( | ) | const [inline] |
Definition at line 223 of file ARMSubtarget.h.
References HasV4TOps.
| bool llvm::ARMSubtarget::hasV5TEOps | ( | ) | const [inline] |
Definition at line 225 of file ARMSubtarget.h.
References HasV5TEOps.
Referenced by llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), LowerPREFETCH(), and llvm::ARMBaseInstrInfo::storeRegToStackSlot().
| bool llvm::ARMSubtarget::hasV5TOps | ( | ) | const [inline] |
Definition at line 224 of file ARMSubtarget.h.
References HasV5TOps.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
| bool llvm::ARMSubtarget::hasV6Ops | ( | ) | const [inline] |
Definition at line 226 of file ARMSubtarget.h.
References HasV6Ops.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::ExpandInlineAsm(), LowerATOMIC_FENCE(), and PerformShiftCombine().
| bool llvm::ARMSubtarget::hasV6T2Ops | ( | ) | const [inline] |
Definition at line 227 of file ARMSubtarget.h.
References HasV6T2Ops.
Referenced by llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerCTTZ(), PerformORCombine(), and useMovt().
| bool llvm::ARMSubtarget::hasV7Ops | ( | ) | const [inline] |
Definition at line 228 of file ARMSubtarget.h.
References HasV7Ops.
Referenced by llvm::ARMTargetLowering::allowsUnalignedMemoryAccesses(), and LowerPREFETCH().
| bool llvm::ARMSubtarget::hasVFP2 | ( | ) | const [inline] |
Definition at line 241 of file ARMSubtarget.h.
References HasVFPv2.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), isLegalAddressImmediate(), and isLegalT2AddressImmediate().
| bool llvm::ARMSubtarget::hasVFP3 | ( | ) | const [inline] |
Definition at line 242 of file ARMSubtarget.h.
References HasVFPv3.
Referenced by llvm::ARMBaseRegisterInfo::getReservedRegs(), and llvm::ARMTargetLowering::isFPImmLegal().
| bool llvm::ARMSubtarget::hasVFP4 | ( | ) | const [inline] |
Definition at line 243 of file ARMSubtarget.h.
References HasVFPv4.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
| bool llvm::ARMSubtarget::hasVMLxForwarding | ( | ) | const [inline] |
Definition at line 254 of file ARMSubtarget.h.
References HasVMLxForwarding.
Referenced by PerformVMULCombine().
| bool llvm::ARMSubtarget::isAAPCS_ABI | ( | ) | const [inline] |
Definition at line 278 of file ARMSubtarget.h.
References ARM_ABI_AAPCS, and TargetABI.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), and llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask().
| bool llvm::ARMSubtarget::isAPCS_ABI | ( | ) | const [inline] |
Definition at line 277 of file ARMSubtarget.h.
References ARM_ABI_APCS, and TargetABI.
| bool llvm::ARMSubtarget::isARClass | ( | ) | const [inline] |
Definition at line 285 of file ARMSubtarget.h.
References IsMClass.
| bool llvm::ARMSubtarget::isCortexA15 | ( | ) | const [inline] |
Definition at line 233 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA15.
Referenced by llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), and isLikeA9().
| bool llvm::ARMSubtarget::isCortexA5 | ( | ) | const [inline] |
Definition at line 230 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA5.
| bool llvm::ARMSubtarget::isCortexA8 | ( | ) | const [inline] |
Definition at line 231 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA8.
Referenced by adjustDefLatency(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::ARMBaseInstrInfo::getNumMicroOps(), and llvm::ARMBaseInstrInfo::getOperandLatency().
| bool llvm::ARMSubtarget::isCortexA9 | ( | ) | const [inline] |
Definition at line 232 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA9.
Referenced by llvm::ARMBaseInstrInfo::getExecutionDomain(), and isLikeA9().
| bool llvm::ARMSubtarget::isCortexM3 | ( | ) | const [inline] |
Definition at line 235 of file ARMSubtarget.h.
References CPUString.
| bool llvm::ARMSubtarget::isCortexR5 | ( | ) | const [inline] |
Definition at line 237 of file ARMSubtarget.h.
References ARMProcFamily, and CortexR5.
| bool llvm::ARMSubtarget::isFPBrccSlow | ( | ) | const [inline] |
Definition at line 255 of file ARMSubtarget.h.
References SlowFPBrcc.
Referenced by canChangeToInt().
| bool llvm::ARMSubtarget::isFPOnlySP | ( | ) | const [inline] |
Definition at line 256 of file ARMSubtarget.h.
References FPOnlySP.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
| bool llvm::ARMSubtarget::isLikeA9 | ( | ) | const [inline] |
Definition at line 236 of file ARMSubtarget.h.
References isCortexA15(), and isCortexA9().
Referenced by adjustDefLatency(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseRegisterInfo::avoidWriteAfterWrite(), llvm::ARMHazardRecognizer::getHazardType(), llvm::ARMBaseInstrInfo::getNumMicroOps(), and llvm::ARMBaseInstrInfo::getOperandLatency().
| bool llvm::ARMSubtarget::isMClass | ( | ) | const [inline] |
Definition at line 284 of file ARMSubtarget.h.
References IsMClass.
| bool llvm::ARMSubtarget::isR9Reserved | ( | ) | const [inline] |
Definition at line 287 of file ARMSubtarget.h.
References IsR9Reserved.
Referenced by llvm::ARMBaseRegisterInfo::getRegPressureLimit(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
| bool llvm::ARMSubtarget::isSwift | ( | ) | const [inline] |
Definition at line 234 of file ARMSubtarget.h.
References ARMProcFamily, and Swift.
Referenced by adjustDefLatency(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), and llvm::ARMBaseInstrInfo::isProfitableToUnpredicate().
| bool llvm::ARMSubtarget::isTargetDarwin | ( | ) | const [inline] |
Definition at line 272 of file ARMSubtarget.h.
References llvm::Triple::isOSDarwin(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), createTLOF(), llvm::ARMAsmPrinter::EmitEndOfAsmFile(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitStartOfAsmFile(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::ARMAsmPrinter::EmitXXStructor(), GVIsIndirectSymbol(), isTargetELF(), and llvm::ARMTargetLowering::LowerOperation().
| bool llvm::ARMSubtarget::isTargetELF | ( | ) | const [inline] |
Definition at line 275 of file ARMSubtarget.h.
References isTargetDarwin().
Referenced by llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), and llvm::ARMAsmPrinter::EmitStartOfAsmFile().
| bool llvm::ARMSubtarget::isTargetIOS | ( | ) | const [inline] |
Definition at line 271 of file ARMSubtarget.h.
References llvm::Triple::getOS(), llvm::Triple::IOS, and TargetTriple.
Referenced by llvm::ARM::createFastISel(), llvm::ARMFrameLowering::emitEpilogue(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask(), llvm::ARMFrameLowering::hasFP(), and llvm::ARMFrameLowering::processFunctionBeforeCalleeSavedScan().
| bool llvm::ARMSubtarget::isTargetLinux | ( | ) | const [inline] |
Definition at line 274 of file ARMSubtarget.h.
References llvm::Triple::getOS(), llvm::Triple::Linux, and TargetTriple.
| bool llvm::ARMSubtarget::isTargetNaCl | ( | ) | const [inline] |
Definition at line 273 of file ARMSubtarget.h.
References llvm::Triple::getOS(), llvm::Triple::NaCl, and TargetTriple.
| bool llvm::ARMSubtarget::isThumb | ( | ) | const [inline] |
Definition at line 280 of file ARMSubtarget.h.
References InThumbMode.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMFrameLowering::emitEpilogue(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getSingleConstraintMatchWeight(), llvm::ARMTargetLowering::isLegalAddImmediate(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerATOMIC_FENCE(), and LowerPREFETCH().
| bool llvm::ARMSubtarget::isThumb1Only | ( | ) | const [inline] |
Definition at line 281 of file ARMSubtarget.h.
References HasThumb2, and InThumbMode.
Referenced by AddCombineTo64bitMLAL(), llvm::ARMBaseInstrInfo::areLoadsFromSameBasePtr(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARM::createFastISel(), Expand64BitShift(), llvm::ARMTargetLowering::getMaximalGlobalOffset(), getMaxInlineSizeThreshold(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), IsSingleInstrConstant(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerPREFETCH(), PerformANDCombine(), PerformMULCombine(), PerformORCombine(), PerformXORCombine(), and llvm::ARMBaseInstrInfo::shouldScheduleLoadsNear().
| bool llvm::ARMSubtarget::isThumb2 | ( | ) | const [inline] |
Definition at line 282 of file ARMSubtarget.h.
References HasThumb2, and InThumbMode.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::ARMTargetLowering::isLegalAddImmediate(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), and LowerPREFETCH().
ParseSubtargetFeatures - Parses features string setting specified subtarget options. Definition of function is auto generated by tblgen.
| bool llvm::ARMSubtarget::prefers32BitThumb | ( | ) | const [inline] |
Definition at line 258 of file ARMSubtarget.h.
References Pref32BitThumb.
| void ARMSubtarget::resetSubtargetFeatures | ( | const MachineFunction * | MF | ) | [virtual] |
Reset the features for the ARM target.
Definition at line 116 of file ARMSubtarget.cpp.
References llvm::X86II::FS, llvm::AttributeSet::FunctionIndex, llvm::AttributeSet::getAttribute(), llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::Attribute::getValueAsString(), llvm::Attribute::hasAttribute(), and llvm::Attribute::None.
Referenced by ARMSubtarget().
| bool llvm::ARMSubtarget::supportsTailCall | ( | ) | const [inline] |
Definition at line 290 of file ARMSubtarget.h.
References SupportsTailCall.
| bool llvm::ARMSubtarget::useFPVMLx | ( | ) | const [inline] |
Definition at line 253 of file ARMSubtarget.h.
References SlowFPVMLx.
| bool llvm::ARMSubtarget::useMovt | ( | ) | const [inline] |
Definition at line 289 of file ARMSubtarget.h.
References hasV6T2Ops(), and UseMovt.
| bool llvm::ARMSubtarget::useMulOps | ( | ) | const [inline] |
Definition at line 252 of file ARMSubtarget.h.
References UseMulOps.
| bool llvm::ARMSubtarget::useNaClTrap | ( | ) | const [inline] |
Definition at line 264 of file ARMSubtarget.h.
References UseNaClTrap.
| bool llvm::ARMSubtarget::useNEONForSinglePrecisionFP | ( | ) | const [inline] |
Definition at line 245 of file ARMSubtarget.h.
References hasNEON(), and UseNEONForSinglePrecisionFP.
Referenced by llvm::ARMTargetLowering::findRepresentativeClass(), and PerformSELECT_CCCombine().
Member Data Documentation
bool llvm::ARMSubtarget::AllowsUnalignedMem [protected] |
AllowsUnalignedMem - If true, the subtarget allows unaligned memory accesses for some types. For details, see ARMTargetLowering::allowsUnalignedMemoryAccesses().
Definition at line 157 of file ARMSubtarget.h.
Referenced by allowsUnalignedMem().
ARMProcFamilyEnum llvm::ARMSubtarget::ARMProcFamily [protected] |
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition at line 38 of file ARMSubtarget.h.
Referenced by isCortexA15(), isCortexA5(), isCortexA8(), isCortexA9(), isCortexR5(), and isSwift().
bool llvm::ARMSubtarget::AvoidCPSRPartialUpdate [protected] |
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR and add false dependency on the previous CPSR setting instruction.
Definition at line 133 of file ARMSubtarget.h.
Referenced by avoidCPSRPartialUpdate().
bool llvm::ARMSubtarget::AvoidMOVsShifterOperand [protected] |
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand (i.e. asr, lsl, lsr).
Definition at line 137 of file ARMSubtarget.h.
Referenced by avoidMOVsShifterOperand().
std::string llvm::ARMSubtarget::CPUString [protected] |
CPUString - String name of used CPU.
Definition at line 174 of file ARMSubtarget.h.
Referenced by getCPUString(), and isCortexM3().
bool llvm::ARMSubtarget::FPOnlySP [protected] |
FPOnlySP - If true, the floating point unit only supports single precision.
Definition at line 149 of file ARMSubtarget.h.
Referenced by isFPOnlySP().
bool llvm::ARMSubtarget::HasD16 [protected] |
HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
Definition at line 110 of file ARMSubtarget.h.
Referenced by hasD16().
bool llvm::ARMSubtarget::HasDataBarrier [protected] |
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition at line 124 of file ARMSubtarget.h.
Referenced by hasDataBarrier().
bool llvm::ARMSubtarget::HasFP16 [protected] |
HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF only so far)
Definition at line 106 of file ARMSubtarget.h.
Referenced by hasFP16().
bool llvm::ARMSubtarget::HasHardwareDivide [protected] |
HasHardwareDivide - True if subtarget supports [su]div.
Definition at line 113 of file ARMSubtarget.h.
Referenced by hasDivide().
bool llvm::ARMSubtarget::HasHardwareDivideInARM [protected] |
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition at line 116 of file ARMSubtarget.h.
Referenced by hasDivideInARMMode().
bool llvm::ARMSubtarget::HasMPExtension [protected] |
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition at line 145 of file ARMSubtarget.h.
Referenced by hasMPExtension().
bool llvm::ARMSubtarget::HasNEON [protected] |
Definition at line 54 of file ARMSubtarget.h.
Referenced by hasNEON().
bool llvm::ARMSubtarget::HasRAS [protected] |
HasRAS - Some processors perform return stack prediction. CodeGen should avoid issue "normal" call instructions to callees which do not return.
Definition at line 141 of file ARMSubtarget.h.
Referenced by hasRAS().
bool llvm::ARMSubtarget::HasT2ExtractPack [protected] |
HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions.
Definition at line 120 of file ARMSubtarget.h.
Referenced by hasT2ExtractPack().
bool llvm::ARMSubtarget::HasThumb2 [protected] |
HasThumb2 - True if Thumb2 instructions are supported.
Definition at line 80 of file ARMSubtarget.h.
Referenced by hasThumb2(), isThumb1Only(), and isThumb2().
bool llvm::ARMSubtarget::HasTrustZone [protected] |
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition at line 152 of file ARMSubtarget.h.
Referenced by hasTrustZone().
bool llvm::ARMSubtarget::HasV4TOps [protected] |
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops - Specify whether target support specific ARM ISA variants.
Definition at line 42 of file ARMSubtarget.h.
Referenced by hasV4TOps().
bool llvm::ARMSubtarget::HasV5TEOps [protected] |
Definition at line 44 of file ARMSubtarget.h.
Referenced by hasV5TEOps().
bool llvm::ARMSubtarget::HasV5TOps [protected] |
Definition at line 43 of file ARMSubtarget.h.
Referenced by hasV5TOps().
bool llvm::ARMSubtarget::HasV6Ops [protected] |
Definition at line 45 of file ARMSubtarget.h.
Referenced by hasV6Ops().
bool llvm::ARMSubtarget::HasV6T2Ops [protected] |
Definition at line 46 of file ARMSubtarget.h.
Referenced by hasV6T2Ops().
bool llvm::ARMSubtarget::HasV7Ops [protected] |
Definition at line 47 of file ARMSubtarget.h.
Referenced by hasV7Ops().
bool llvm::ARMSubtarget::HasVFPv2 [protected] |
HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what floating point ISAs are supported.
Definition at line 51 of file ARMSubtarget.h.
Referenced by hasVFP2().
bool llvm::ARMSubtarget::HasVFPv3 [protected] |
Definition at line 52 of file ARMSubtarget.h.
Referenced by hasVFP3().
bool llvm::ARMSubtarget::HasVFPv4 [protected] |
Definition at line 53 of file ARMSubtarget.h.
Referenced by hasVFP4().
bool llvm::ARMSubtarget::HasVMLxForwarding [protected] |
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla being issued back to back.
Definition at line 71 of file ARMSubtarget.h.
Referenced by hasVMLxForwarding().
InstrItineraryData llvm::ARMSubtarget::InstrItins [protected] |
Selected instruction itineraries (one entry per itinerary class.)
Definition at line 183 of file ARMSubtarget.h.
Referenced by getInstrItineraryData().
bool llvm::ARMSubtarget::InThumbMode [protected] |
InThumbMode - True if compiling for Thumb, false for ARM.
Definition at line 77 of file ARMSubtarget.h.
Referenced by isThumb(), isThumb1Only(), and isThumb2().
bool llvm::ARMSubtarget::IsMClass [protected] |
IsMClass - True if the subtarget belongs to the 'M' profile of CPUs - v6m, v7m for example.
Definition at line 84 of file ARMSubtarget.h.
Referenced by isARClass(), and isMClass().
bool llvm::ARMSubtarget::IsR9Reserved [protected] |
IsR9Reserved - True if R9 is a not available as general purpose register.
Definition at line 93 of file ARMSubtarget.h.
Referenced by isR9Reserved().
bool llvm::ARMSubtarget::NoARM [protected] |
NoARM - True if subtarget does not support ARM mode execution.
Definition at line 87 of file ARMSubtarget.h.
Referenced by hasARMOps().
const TargetOptions& llvm::ARMSubtarget::Options [protected] |
Options passed via command line that could influence the target.
Definition at line 186 of file ARMSubtarget.h.
bool llvm::ARMSubtarget::PostRAScheduler [protected] |
PostRAScheduler - True if using post-register-allocation scheduler.
Definition at line 90 of file ARMSubtarget.h.
Referenced by enablePostRAScheduler().
bool llvm::ARMSubtarget::Pref32BitThumb [protected] |
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones.
Definition at line 128 of file ARMSubtarget.h.
Referenced by prefers32BitThumb().
const MCSchedModel* llvm::ARMSubtarget::SchedModel [protected] |
SchedModel - Processor specific instruction costs.
Definition at line 180 of file ARMSubtarget.h.
Referenced by getMispredictionPenalty().
bool llvm::ARMSubtarget::SlowFPBrcc [protected] |
SlowFPBrcc - True if floating point compare + branch is slow.
Definition at line 74 of file ARMSubtarget.h.
Referenced by isFPBrccSlow().
bool llvm::ARMSubtarget::SlowFPVMLx [protected] |
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instructions are slow (if so, don't use them).
Definition at line 67 of file ARMSubtarget.h.
Referenced by useFPVMLx().
unsigned llvm::ARMSubtarget::stackAlignment [protected] |
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.
Definition at line 171 of file ARMSubtarget.h.
Referenced by getStackAlignment().
bool llvm::ARMSubtarget::SupportsTailCall [protected] |
SupportsTailCall - True if the OS supports tail call. The dynamic linker must be able to synthesize call stubs for interworking between ARM and Thumb.
Definition at line 102 of file ARMSubtarget.h.
Referenced by supportsTailCall().
| enum { ... } llvm::ARMSubtarget::TargetABI |
Referenced by isAAPCS_ABI(), and isAPCS_ABI().
Triple llvm::ARMSubtarget::TargetTriple [protected] |
TargetTriple - What processor and OS we're targeting.
Definition at line 177 of file ARMSubtarget.h.
Referenced by getTargetTriple(), isTargetDarwin(), isTargetIOS(), isTargetLinux(), and isTargetNaCl().
| enum { ... } llvm::ARMSubtarget::TargetType |
bool llvm::ARMSubtarget::Thumb2DSP [protected] |
Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith and such) instructions in Thumb2 code.
Definition at line 161 of file ARMSubtarget.h.
Referenced by hasThumb2DSP().
bool llvm::ARMSubtarget::UnsafeFPMath [protected] |
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition at line 167 of file ARMSubtarget.h.
bool llvm::ARMSubtarget::UseMovt [protected] |
UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit imms (including global addresses).
Definition at line 97 of file ARMSubtarget.h.
Referenced by useMovt().
bool llvm::ARMSubtarget::UseMulOps [protected] |
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.
Definition at line 63 of file ARMSubtarget.h.
Referenced by useMulOps().
bool llvm::ARMSubtarget::UseNaClTrap [protected] |
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition at line 164 of file ARMSubtarget.h.
Referenced by useNaClTrap().
bool llvm::ARMSubtarget::UseNEONForSinglePrecisionFP [protected] |
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified. Use the method useNEONForSinglePrecisionFP() to determine if NEON should actually be used.
Definition at line 59 of file ARMSubtarget.h.
Referenced by useNEONForSinglePrecisionFP().
The documentation for this class was generated from the following files:
1.7.5.1