LLVM  9.0.0svn
LanaiAsmBackend.cpp
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1 //===-- LanaiAsmBackend.cpp - Lanai Assembler Backend ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "LanaiFixupKinds.h"
11 #include "llvm/MC/MCAsmBackend.h"
12 #include "llvm/MC/MCAssembler.h"
13 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCObjectWriter.h"
20 
21 using namespace llvm;
22 
23 // Prepare value for the target space
24 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
25  switch (Kind) {
26  case FK_Data_1:
27  case FK_Data_2:
28  case FK_Data_4:
29  case FK_Data_8:
30  return Value;
37  return Value;
38  default:
39  llvm_unreachable("Unknown fixup kind!");
40  }
41 }
42 
43 namespace {
44 class LanaiAsmBackend : public MCAsmBackend {
45  Triple::OSType OSType;
46 
47 public:
48  LanaiAsmBackend(const Target &T, Triple::OSType OST)
49  : MCAsmBackend(support::big), OSType(OST) {}
50 
51  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
53  uint64_t Value, bool IsResolved,
54  const MCSubtargetInfo *STI) const override;
55 
56  std::unique_ptr<MCObjectTargetWriter>
57  createObjectTargetWriter() const override;
58 
59  // No instruction requires relaxation
60  bool fixupNeedsRelaxation(const MCFixup & /*Fixup*/, uint64_t /*Value*/,
61  const MCRelaxableFragment * /*DF*/,
62  const MCAsmLayout & /*Layout*/) const override {
63  return false;
64  }
65 
66  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
67 
68  unsigned getNumFixupKinds() const override {
70  }
71 
72  bool mayNeedRelaxation(const MCInst & /*Inst*/,
73  const MCSubtargetInfo &STI) const override {
74  return false;
75  }
76 
77  void relaxInstruction(const MCInst & /*Inst*/,
78  const MCSubtargetInfo & /*STI*/,
79  MCInst & /*Res*/) const override {}
80 
81  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
82 };
83 
84 bool LanaiAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
85  if ((Count % 4) != 0)
86  return false;
87 
88  for (uint64_t i = 0; i < Count; i += 4)
89  OS.write("\x15\0\0\0", 4);
90 
91  return true;
92 }
93 
94 void LanaiAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
95  const MCValue &Target,
97  bool /*IsResolved*/,
98  const MCSubtargetInfo * /*STI*/) const {
99  MCFixupKind Kind = Fixup.getKind();
100  Value = adjustFixupValue(static_cast<unsigned>(Kind), Value);
101 
102  if (!Value)
103  return; // This value doesn't change the encoding
104 
105  // Where in the object and where the number of bytes that need
106  // fixing up
107  unsigned Offset = Fixup.getOffset();
108  unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
109  unsigned FullSize = 4;
110 
111  // Grab current value, if any, from bits.
112  uint64_t CurVal = 0;
113 
114  // Load instruction and apply value
115  for (unsigned i = 0; i != NumBytes; ++i) {
116  unsigned Idx = (FullSize - 1 - i);
117  CurVal |= static_cast<uint64_t>(static_cast<uint8_t>(Data[Offset + Idx]))
118  << (i * 8);
119  }
120 
121  uint64_t Mask =
122  (static_cast<uint64_t>(-1) >> (64 - getFixupKindInfo(Kind).TargetSize));
123  CurVal |= Value & Mask;
124 
125  // Write out the fixed up bytes back to the code/data bits.
126  for (unsigned i = 0; i != NumBytes; ++i) {
127  unsigned Idx = (FullSize - 1 - i);
128  Data[Offset + Idx] = static_cast<uint8_t>((CurVal >> (i * 8)) & 0xff);
129  }
130 }
131 
132 std::unique_ptr<MCObjectTargetWriter>
133 LanaiAsmBackend::createObjectTargetWriter() const {
135 }
136 
137 const MCFixupKindInfo &
138 LanaiAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
139  static const MCFixupKindInfo Infos[Lanai::NumTargetFixupKinds] = {
140  // This table *must* be in same the order of fixup_* kinds in
141  // LanaiFixupKinds.h.
142  // Note: The number of bits indicated here are assumed to be contiguous.
143  // This does not hold true for LANAI_21 and LANAI_21_F which are applied
144  // to bits 0x7cffff and 0x7cfffc, respectively. Since the 'bits' counts
145  // here are used only for cosmetic purposes, we set the size to 16 bits
146  // for these 21-bit relocation as llvm/lib/MC/MCAsmStreamer.cpp checks
147  // no bits are set in the fixup range.
148  //
149  // name offset bits flags
150  {"FIXUP_LANAI_NONE", 0, 32, 0},
151  {"FIXUP_LANAI_21", 16, 16 /*21*/, 0},
152  {"FIXUP_LANAI_21_F", 16, 16 /*21*/, 0},
153  {"FIXUP_LANAI_25", 7, 25, 0},
154  {"FIXUP_LANAI_32", 0, 32, 0},
155  {"FIXUP_LANAI_HI16", 16, 16, 0},
156  {"FIXUP_LANAI_LO16", 16, 16, 0}};
157 
158  if (Kind < FirstTargetFixupKind)
159  return MCAsmBackend::getFixupKindInfo(Kind);
160 
161  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
162  "Invalid kind!");
163  return Infos[Kind - FirstTargetFixupKind];
164 }
165 
166 } // namespace
167 
169  const MCSubtargetInfo &STI,
170  const MCRegisterInfo & /*MRI*/,
171  const MCTargetOptions & /*Options*/) {
172  const Triple &TT = STI.getTargetTriple();
173  if (!TT.isOSBinFormatELF())
174  llvm_unreachable("OS not supported");
175 
176  return new LanaiAsmBackend(T, TT.getOS());
177 }
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This represents an "assembler immediate".
Definition: MCValue.h:39
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:618
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:304
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:74
const Triple & getTargetTriple() const
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
A four-byte fixup.
Definition: MCFixup.h:26
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:290
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
std::unique_ptr< MCObjectTargetWriter > createLanaiELFObjectWriter(uint8_t OSABI)
uint32_t getOffset() const
Definition: MCFixup.h:125
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:24
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
raw_ostream & write(unsigned char C)
PowerPC TLS Dynamic Call Fixup
static unsigned adjustFixupValue(unsigned Kind, uint64_t Value)
Target - Wrapper for Target specific information.
Generic base class for all target subtargets.
A eight-byte fixup.
Definition: MCFixup.h:27
Target independent information on a fixup kind.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
A two-byte fixup.
Definition: MCFixup.h:25
MCFixupKind getKind() const
Definition: MCFixup.h:123
MCAsmBackend * createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)