LLVM  9.0.0svn
SystemZDisassembler.cpp
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1 //===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "SystemZ.h"
13 #include "llvm/MC/MCInst.h"
17 #include <cassert>
18 #include <cstdint>
19 
20 using namespace llvm;
21 
22 #define DEBUG_TYPE "systemz-disassembler"
23 
25 
26 namespace {
27 
28 class SystemZDisassembler : public MCDisassembler {
29 public:
30  SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
31  : MCDisassembler(STI, Ctx) {}
32  ~SystemZDisassembler() override = default;
33 
34  DecodeStatus getInstruction(MCInst &instr, uint64_t &Size,
35  ArrayRef<uint8_t> Bytes, uint64_t Address,
36  raw_ostream &VStream,
37  raw_ostream &CStream) const override;
38 };
39 
40 } // end anonymous namespace
41 
43  const MCSubtargetInfo &STI,
44  MCContext &Ctx) {
45  return new SystemZDisassembler(STI, Ctx);
46 }
47 
49  // Register the disassembler.
52 }
53 
54 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
55 /// immediate Value in the MCInst.
56 ///
57 /// @param Value - The immediate Value, has had any PC adjustment made by
58 /// the caller.
59 /// @param isBranch - If the instruction is a branch instruction
60 /// @param Address - The starting address of the instruction
61 /// @param Offset - The byte offset to this immediate in the instruction
62 /// @param Width - The byte width of this immediate in the instruction
63 ///
64 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
65 /// called then that function is called to get any symbolic information for the
66 /// immediate in the instruction using the Address, Offset and Width. If that
67 /// returns non-zero then the symbolic information it returns is used to create
68 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
69 /// returns zero and isBranch is true then a symbol look up for immediate Value
70 /// is done and if a symbol is found an MCExpr is created with that, else
71 /// an MCExpr with the immediate Value is created. This function returns true
72 /// if it adds an operand to the MCInst and false otherwise.
73 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
74  uint64_t Address, uint64_t Offset,
75  uint64_t Width, MCInst &MI,
76  const void *Decoder) {
77  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
78  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
79  Offset, Width);
80 }
81 
82 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
83  const unsigned *Regs, unsigned Size) {
84  assert(RegNo < Size && "Invalid register");
85  RegNo = Regs[RegNo];
86  if (RegNo == 0)
87  return MCDisassembler::Fail;
88  Inst.addOperand(MCOperand::createReg(RegNo));
90 }
91 
92 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
93  uint64_t Address,
94  const void *Decoder) {
95  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
96 }
97 
98 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
99  uint64_t Address,
100  const void *Decoder) {
101  return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
102 }
103 
104 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
105  uint64_t Address,
106  const void *Decoder) {
107  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
108 }
109 
110 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
111  uint64_t Address,
112  const void *Decoder) {
113  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
114 }
115 
116 static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
117  uint64_t Address,
118  const void *Decoder) {
119  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
120 }
121 
122 static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
123  uint64_t Address,
124  const void *Decoder) {
125  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
126 }
127 
128 static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
129  uint64_t Address,
130  const void *Decoder) {
131  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16);
132 }
133 
134 static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
135  uint64_t Address,
136  const void *Decoder) {
137  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16);
138 }
139 
140 static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
141  uint64_t Address,
142  const void *Decoder) {
143  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32);
144 }
145 
146 static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
147  uint64_t Address,
148  const void *Decoder) {
149  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32);
150 }
151 
152 static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
153  uint64_t Address,
154  const void *Decoder) {
155  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32);
156 }
157 
158 static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
159  uint64_t Address,
160  const void *Decoder) {
161  return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16);
162 }
163 
164 static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
165  uint64_t Address,
166  const void *Decoder) {
167  return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16);
168 }
169 
170 template<unsigned N>
171 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
172  if (!isUInt<N>(Imm))
173  return MCDisassembler::Fail;
174  Inst.addOperand(MCOperand::createImm(Imm));
176 }
177 
178 template<unsigned N>
179 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
180  if (!isUInt<N>(Imm))
181  return MCDisassembler::Fail;
182  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
184 }
185 
186 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
187  uint64_t Address, const void *Decoder) {
188  return decodeUImmOperand<1>(Inst, Imm);
189 }
190 
191 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm,
192  uint64_t Address, const void *Decoder) {
193  return decodeUImmOperand<2>(Inst, Imm);
194 }
195 
196 static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm,
197  uint64_t Address, const void *Decoder) {
198  return decodeUImmOperand<3>(Inst, Imm);
199 }
200 
201 static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm,
202  uint64_t Address, const void *Decoder) {
203  return decodeUImmOperand<4>(Inst, Imm);
204 }
205 
206 static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm,
207  uint64_t Address, const void *Decoder) {
208  return decodeUImmOperand<6>(Inst, Imm);
209 }
210 
211 static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm,
212  uint64_t Address, const void *Decoder) {
213  return decodeUImmOperand<8>(Inst, Imm);
214 }
215 
216 static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm,
217  uint64_t Address, const void *Decoder) {
218  return decodeUImmOperand<12>(Inst, Imm);
219 }
220 
221 static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm,
222  uint64_t Address, const void *Decoder) {
223  return decodeUImmOperand<16>(Inst, Imm);
224 }
225 
226 static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm,
227  uint64_t Address, const void *Decoder) {
228  return decodeUImmOperand<32>(Inst, Imm);
229 }
230 
231 static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm,
232  uint64_t Address, const void *Decoder) {
233  return decodeSImmOperand<8>(Inst, Imm);
234 }
235 
236 static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm,
237  uint64_t Address, const void *Decoder) {
238  return decodeSImmOperand<16>(Inst, Imm);
239 }
240 
241 static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm,
242  uint64_t Address, const void *Decoder) {
243  return decodeSImmOperand<32>(Inst, Imm);
244 }
245 
246 template<unsigned N>
247 static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
248  uint64_t Address,
249  bool isBranch,
250  const void *Decoder) {
251  assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
252  uint64_t Value = SignExtend64<N>(Imm) * 2 + Address;
253 
254  if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, N / 8,
255  Inst, Decoder))
256  Inst.addOperand(MCOperand::createImm(Value));
257 
259 }
260 
261 static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm,
262  uint64_t Address,
263  const void *Decoder) {
264  return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder);
265 }
266 
267 static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm,
268  uint64_t Address,
269  const void *Decoder) {
270  return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder);
271 }
272 
273 static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm,
274  uint64_t Address,
275  const void *Decoder) {
276  return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder);
277 }
278 
279 static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm,
280  uint64_t Address,
281  const void *Decoder) {
282  return decodePCDBLOperand<32>(Inst, Imm, Address, true, Decoder);
283 }
284 
285 static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm,
286  uint64_t Address,
287  const void *Decoder) {
288  return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
289 }
290 
292  const unsigned *Regs) {
293  uint64_t Base = Field >> 12;
294  uint64_t Disp = Field & 0xfff;
295  assert(Base < 16 && "Invalid BDAddr12");
296  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
297  Inst.addOperand(MCOperand::createImm(Disp));
299 }
300 
302  const unsigned *Regs) {
303  uint64_t Base = Field >> 20;
304  uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
305  assert(Base < 16 && "Invalid BDAddr20");
306  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
307  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
309 }
310 
312  const unsigned *Regs) {
313  uint64_t Index = Field >> 16;
314  uint64_t Base = (Field >> 12) & 0xf;
315  uint64_t Disp = Field & 0xfff;
316  assert(Index < 16 && "Invalid BDXAddr12");
317  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
318  Inst.addOperand(MCOperand::createImm(Disp));
319  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
321 }
322 
324  const unsigned *Regs) {
325  uint64_t Index = Field >> 24;
326  uint64_t Base = (Field >> 20) & 0xf;
327  uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
328  assert(Index < 16 && "Invalid BDXAddr20");
329  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
330  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
331  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
333 }
334 
336  const unsigned *Regs) {
337  uint64_t Length = Field >> 16;
338  uint64_t Base = (Field >> 12) & 0xf;
339  uint64_t Disp = Field & 0xfff;
340  assert(Length < 16 && "Invalid BDLAddr12Len4");
341  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
342  Inst.addOperand(MCOperand::createImm(Disp));
343  Inst.addOperand(MCOperand::createImm(Length + 1));
345 }
346 
348  const unsigned *Regs) {
349  uint64_t Length = Field >> 16;
350  uint64_t Base = (Field >> 12) & 0xf;
351  uint64_t Disp = Field & 0xfff;
352  assert(Length < 256 && "Invalid BDLAddr12Len8");
353  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
354  Inst.addOperand(MCOperand::createImm(Disp));
355  Inst.addOperand(MCOperand::createImm(Length + 1));
357 }
358 
360  const unsigned *Regs) {
361  uint64_t Length = Field >> 16;
362  uint64_t Base = (Field >> 12) & 0xf;
363  uint64_t Disp = Field & 0xfff;
364  assert(Length < 16 && "Invalid BDRAddr12");
365  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
366  Inst.addOperand(MCOperand::createImm(Disp));
367  Inst.addOperand(MCOperand::createReg(Regs[Length]));
369 }
370 
372  const unsigned *Regs) {
373  uint64_t Index = Field >> 16;
374  uint64_t Base = (Field >> 12) & 0xf;
375  uint64_t Disp = Field & 0xfff;
376  assert(Index < 32 && "Invalid BDVAddr12");
377  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
378  Inst.addOperand(MCOperand::createImm(Disp));
381 }
382 
384  uint64_t Address,
385  const void *Decoder) {
386  return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs);
387 }
388 
390  uint64_t Address,
391  const void *Decoder) {
392  return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs);
393 }
394 
396  uint64_t Address,
397  const void *Decoder) {
398  return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
399 }
400 
402  uint64_t Address,
403  const void *Decoder) {
404  return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
405 }
406 
408  uint64_t Address,
409  const void *Decoder) {
410  return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
411 }
412 
414  uint64_t Address,
415  const void *Decoder) {
416  return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
417 }
418 
420  uint64_t Field,
421  uint64_t Address,
422  const void *Decoder) {
423  return decodeBDLAddr12Len4Operand(Inst, Field, SystemZMC::GR64Regs);
424 }
425 
427  uint64_t Field,
428  uint64_t Address,
429  const void *Decoder) {
430  return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs);
431 }
432 
434  uint64_t Field,
435  uint64_t Address,
436  const void *Decoder) {
437  return decodeBDRAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
438 }
439 
441  uint64_t Address,
442  const void *Decoder) {
443  return decodeBDVAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
444 }
445 
446 #include "SystemZGenDisassemblerTables.inc"
447 
448 DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
449  ArrayRef<uint8_t> Bytes,
450  uint64_t Address,
451  raw_ostream &OS,
452  raw_ostream &CS) const {
453  // Get the first two bytes of the instruction.
454  Size = 0;
455  if (Bytes.size() < 2)
456  return MCDisassembler::Fail;
457 
458  // The top 2 bits of the first byte specify the size.
459  const uint8_t *Table;
460  if (Bytes[0] < 0x40) {
461  Size = 2;
462  Table = DecoderTable16;
463  } else if (Bytes[0] < 0xc0) {
464  Size = 4;
465  Table = DecoderTable32;
466  } else {
467  Size = 6;
468  Table = DecoderTable48;
469  }
470 
471  // Read any remaining bytes.
472  if (Bytes.size() < Size)
473  return MCDisassembler::Fail;
474 
475  // Construct the instruction.
476  uint64_t Inst = 0;
477  for (uint64_t I = 0; I < Size; ++I)
478  Inst = (Inst << 8) | Bytes[I];
479 
480  return decodeInstruction(Table, MI, Inst, Address, this, STI);
481 }
static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
const unsigned GR32Regs[16]
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, bool isBranch, const void *Decoder)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const unsigned FP128Regs[16]
static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
const unsigned FP32Regs[16]
static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
const unsigned VR64Regs[32]
static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
const unsigned AR32Regs[16]
static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
const unsigned GRH32Regs[16]
static MCDisassembler * createSystemZDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Context object for machine code objects.
Definition: MCContext.h:62
static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const void *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
const unsigned CR64Regs[16]
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm)
static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
const unsigned FP64Regs[16]
const unsigned GR128Regs[16]
const unsigned GR64Regs[16]
static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Target - Wrapper for Target specific information.
static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Target & getTheSystemZTarget()
static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Generic base class for all target subtargets.
static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm)
const unsigned VR32Regs[32]
uint32_t Size
Definition: Profile.cpp:46
static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
void LLVMInitializeSystemZDisassembler()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
LLVM Value Representation.
Definition: Value.h:72
static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size)
static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
const unsigned VR128Regs[32]
static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)