28 return CF->isZero() && CF->isNegative();
30 return CF->isZero() && !CF->isNegative();
46 return C->isMinusOne();
48 return C->isMaxValue(
true);
50 return C->isMinValue(
true);
52 return C->isMaxValue(
false);
54 return C->isMinValue(
false);
67 return !CF->isNegative() && CF->isInfinity();
70 return CF->isNegative() && CF->isInfinity();
88 return C->isAllOnesValue();
92 return C->isMinValue(
true);
94 return C->isMaxValue(
true);
96 return C->isMinValue(
false);
98 return C->isMaxValue(
false);
113 if (isSaturating(RMWI) &&
121 "AtomicRMWs don't make sense with Unordered or NotAtomic");
123 if (!isIdempotentRMW(RMWI))
This file provides internal interfaces used to implement the InstCombine.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
an instruction that atomically reads a memory location, combines it with another value,...
bool isVolatile() const
Return true if this is a RMW on a volatile memory location.
@ Min
*p = old <signed v ? old : v
@ Max
*p = old >signed v ? old : v
@ UMin
*p = old <unsigned v ? old : v
@ FMin
*p = minnum(old, v) minnum matches the behavior of llvm.minnum.
@ UMax
*p = old >unsigned v ? old : v
@ FMax
*p = maxnum(old, v) maxnum matches the behavior of llvm.maxnum.
void setOperation(BinOp Operation)
BinOp getOperation() const
AtomicOrdering getOrdering() const
Returns the ordering constraint of this rmw instruction.
static Constant * getNegativeZero(Type *Ty)
Instruction * visitAtomicRMWInst(AtomicRMWInst &SI)
Instruction * replaceOperand(Instruction &I, unsigned OpNum, Value *V)
Replace operand of instruction and add old operand to the worklist.
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
bool isIntegerTy() const
True if this is an instance of IntegerType.
Type * getType() const
All values are typed, get the type of this value.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.