14#ifndef LLVM_LIB_CODEGEN_REGISTERCOALESCER_H
15#define LLVM_LIB_CODEGEN_REGISTERCOALESCER_H
22class TargetRegisterClass;
23class TargetRegisterInfo;
48 bool CrossClass =
false;
66 :
TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {}
81 bool isPhys()
const {
return !NewRC; }
unsigned const TargetRegisterInfo * TRI
A helper class for register coalescers.
unsigned getDstIdx() const
Return the subregister index that DstReg will be coalesced into, or 0.
bool isFlipped() const
Return true when getSrcReg is the register being defined by the original copy instruction.
bool isPartial() const
Return true if the original copy instruction did not copy the full register, but was a subreg operati...
bool flip()
Swap SrcReg and DstReg.
bool isPhys() const
Return true if DstReg is a physical register.
bool isCrossClass() const
Return true if DstReg is virtual and NewRC is a smaller register class than DstReg's.
Register getDstReg() const
Return the register (virtual or physical) that will remain after coalescing.
bool isCoalescable(const MachineInstr *) const
Return true if MI is a copy instruction that will become an identity copy after coalescing.
CoalescerPair(const TargetRegisterInfo &tri)
CoalescerPair(Register VirtReg, MCRegister PhysReg, const TargetRegisterInfo &tri)
Create a CoalescerPair representing a virtreg-to-physreg copy.
const TargetRegisterClass * getNewRC() const
Return the register class of the coalesced register.
bool setRegisters(const MachineInstr *)
Set registers to match the copy instruction MI.
unsigned getSrcIdx() const
Return the subregister index that SrcReg will be coalesced into, or 0.
Register getSrcReg() const
Return the virtual register that will be coalesced away.
Wrapper class representing physical registers. Should be passed by value.
Representation of each machine instruction.
Wrapper class representing virtual and physical registers.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.