16#ifndef LLVM_MCA_STAGES_RETIRESTAGE_H
17#define LLVM_MCA_STAGES_RETIRESTAGE_H
39 : RCU(R), PRF(
F), LSU(LS) {}
A Load/Store unit class that models load/store queues and that implements a simple weak memory consis...
Legalize the Machine IR a function s Machine IR
This file defines a register mapping file class.
This file simulates the hardware responsible for retiring instructions.
This file defines the SmallVector class.
This file defines a stage.
Lightweight error class with error context and mandatory checking.
An InstRef contains both a SourceMgr index and Instruction pair.
Abstract base interface for LS (load/store) units in llvm-mca.
Manages hardware register files, and tracks register definitions for register renaming purposes.
Error cycleEnd() override
Called once at the end of each cycle.
void notifyInstructionRetired(const InstRef &IR) const
Error cycleStart() override
Called once at the start of each cycle.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)
This is an optimization pass for GlobalISel generic memory operations.
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...