33#include "llvm/IR/IntrinsicsSPIRV.h"
35#define GET_GICOMBINER_DEPS
36#include "SPIRVGenPreLegalizeGICombiner.inc"
37#undef GET_GICOMBINER_DEPS
39#define DEBUG_TYPE "spirv-prelegalizer-combiner"
46#define GET_GICOMBINER_TYPES
47#include "SPIRVGenPreLegalizeGICombiner.inc"
48#undef GET_GICOMBINER_TYPES
59 if (
MI.getOpcode() != TargetOpcode::G_INTRINSIC ||
66 if (!SubInstr || SubInstr->
getOpcode() != TargetOpcode::G_FSUB)
75 Register SubDestReg =
MI.getOperand(2).getReg();
82 Register ResultReg =
MI.getOperand(0).getReg();
89 BuildMI(
MBB, InsertPt,
DL,
B.getTII().get(TargetOpcode::G_INTRINSIC));
103 for (
auto *MIToErase : UsesToErase) {
105 MIToErase->eraseFromParent();
108 RemoveAllUses(SubDestReg);
113class SPIRVPreLegalizerCombinerImpl :
public Combiner {
115 const CombinerHelper Helper;
116 const SPIRVPreLegalizerCombinerImplRuleConfig &RuleConfig;
117 const SPIRVSubtarget &STI;
120 SPIRVPreLegalizerCombinerImpl(
121 MachineFunction &MF, CombinerInfo &CInfo,
const TargetPassConfig *TPC,
122 GISelValueTracking &VT, GISelCSEInfo *CSEInfo,
123 const SPIRVPreLegalizerCombinerImplRuleConfig &RuleConfig,
124 const SPIRVSubtarget &STI, MachineDominatorTree *MDT,
125 const LegalizerInfo *LI);
127 static const char *
getName() {
return "SPIRVPreLegalizerCombiner"; }
129 bool tryCombineAll(MachineInstr &
I)
const override;
131 bool tryCombineAllImpl(MachineInstr &
I)
const;
134#define GET_GICOMBINER_CLASS_MEMBERS
135#include "SPIRVGenPreLegalizeGICombiner.inc"
136#undef GET_GICOMBINER_CLASS_MEMBERS
139#define GET_GICOMBINER_IMPL
140#include "SPIRVGenPreLegalizeGICombiner.inc"
141#undef GET_GICOMBINER_IMPL
143SPIRVPreLegalizerCombinerImpl::SPIRVPreLegalizerCombinerImpl(
146 const SPIRVPreLegalizerCombinerImplRuleConfig &RuleConfig,
149 :
Combiner(MF, CInfo, TPC, &VT, CSEInfo),
150 Helper(Observer,
B,
true, &VT, MDT, LI),
151 RuleConfig(RuleConfig), STI(STI),
153#include
"SPIRVGenPreLegalizeGICombiner.inc"
158bool SPIRVPreLegalizerCombinerImpl::tryCombineAll(
MachineInstr &
MI)
const {
159 return tryCombineAllImpl(
MI);
165class SPIRVPreLegalizerCombiner :
public MachineFunctionPass {
169 SPIRVPreLegalizerCombiner();
171 StringRef getPassName()
const override {
return "SPIRVPreLegalizerCombiner"; }
173 bool runOnMachineFunction(MachineFunction &MF)
override;
175 void getAnalysisUsage(AnalysisUsage &AU)
const override;
178 SPIRVPreLegalizerCombinerImplRuleConfig RuleConfig;
183void SPIRVPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU)
const {
187 AU.
addRequired<GISelValueTrackingAnalysisLegacy>();
194SPIRVPreLegalizerCombiner::SPIRVPreLegalizerCombiner()
195 : MachineFunctionPass(
ID) {
196 if (!RuleConfig.parseCommandLineOption())
200bool SPIRVPreLegalizerCombiner::runOnMachineFunction(
MachineFunction &MF) {
203 auto &TPC = getAnalysis<TargetPassConfig>();
206 const auto *LI =
ST.getLegalizerInfo();
212 &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
214 &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
216 nullptr, EnableOpt,
F.hasOptSize(),
219 CInfo.MaxIterations = 1;
223 CInfo.EnableFullDCE =
false;
224 SPIRVPreLegalizerCombinerImpl Impl(MF, CInfo, &TPC, *VT,
nullptr,
225 RuleConfig, ST, MDT, LI);
226 return Impl.combineMachineInstrs();
229char SPIRVPreLegalizerCombiner::ID = 0;
231 "Combine SPIRV machine instrs before legalization",
false,
236 "Combine SPIRV machine instrs before legalization",
false,
241 return new SPIRVPreLegalizerCombiner();
unsigned const MachineRegisterInfo * MRI
#define GET_GICOMBINER_CONSTRUCTOR_INITS
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Provides analysis for continuously CSEing during GISel passes.
This contains common combine transformations that may be used in a combine pass,or by the target else...
Option class for Targets to specify which operations are combined how and when.
This contains the base class for all Combiners generated by TableGen.
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static StringRef getName(Value *V)
Target-Independent Code Generator Pass Configuration Options pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelValueTrackingInfoAnal...
MachineInstrBundleIterator< MachineInstr > iterator
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Helper class to build MachineInstr.
const MachineInstrBuilder & addIntrinsicID(Intrinsic::ID ID) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
LLVM_ABI void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
void invalidateMachineInstr(MachineInstr *MI)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Target-Independent Code Generator Pass Configuration Options.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass * createSPIRVPreLegalizerCombiner()
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
iterator_range< pointer_iterator< WrappedIteratorT > > make_pointer_range(RangeT &&Range)
@ SinglePass
Enables Observer-based DCE and additional heuristics that retry combining defined and used instructio...