14#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
15#define LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
30class InstrItineraryData;
66 if (isa<ConstantSDNode>(
Node))
return true;
67 if (isa<ConstantFPSDNode>(
Node))
return true;
68 if (isa<RegisterSDNode>(
Node))
return true;
69 if (isa<RegisterMaskSDNode>(
Node))
return true;
70 if (isa<GlobalAddressSDNode>(
Node))
return true;
71 if (isa<BasicBlockSDNode>(
Node))
return true;
72 if (isa<FrameIndexSDNode>(
Node))
return true;
73 if (isa<ConstantPoolSDNode>(
Node))
return true;
74 if (isa<TargetIndexSDNode>(
Node))
return true;
75 if (isa<JumpTableSDNode>(
Node))
return true;
76 if (isa<ExternalSymbolSDNode>(
Node))
return true;
77 if (isa<MCSymbolSDNode>(
Node))
return true;
78 if (isa<BlockAddressSDNode>(
Node))
return true;
80 isa<MDNodeSDNode>(
Node))
return true;
108 unsigned OpIdx,
SDep& dep)
const;
126 void dump()
const override;
142 unsigned NodeNumDefs = 0;
166 void InitNodeNumDefs();
184 void BuildSchedUnits();
185 void AddSchedEdges();
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Itinerary data supplied by a subtarget to be used by a target.
Represents one node in the SelectionDAG.
Scheduling unit. This is a node in the scheduling DAG.
RegDefIter - In place iteration over the values defined by an SUnit.
const SDNode * GetNode() const
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
virtual void getCustomGraphFeatures(GraphWriter< ScheduleDAG * > &GW) const
SUnit * newSUnit(SDNode *N)
NewSUnit - Creates a new SUnit and return a ptr to it.
void VerifyScheduledSequence(bool isBottomUp)
VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of sc...
virtual void Schedule()=0
Schedule - Order nodes according to selected style, filling in the Sequence member.
virtual void computeLatency(SUnit *SU)
computeLatency - Compute node latency.
std::string getDAGName() const override
Return the basic block label.
virtual MachineBasicBlock * EmitSchedule(MachineBasicBlock::iterator &InsertPos)
EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Se...
~ScheduleDAGSDNodes() override=default
virtual bool forceUnitLatencies() const
ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one.
std::string getGraphNodeLabel(const SUnit *SU) const override
Returns a label for an SUnit node in a visualization of the ScheduleDAG.
void BuildSchedGraph(AAResults *AA)
BuildSchedGraph - Build the SUnit graph from the selection dag that we are input.
static bool isPassiveNode(SDNode *Node)
isPassiveNode - Return true if the node is a non-scheduled leaf.
const InstrItineraryData * InstrItins
void InitNumRegDefsLeft(SUnit *SU)
InitNumRegDefsLeft - Determine the # of regs defined by this node.
std::vector< SUnit * > Sequence
The schedule. Null SUnit*'s represent noop instructions.
void Run(SelectionDAG *dag, MachineBasicBlock *bb)
Run - perform scheduling.
void dump() const override
void dumpNode(const SUnit &SU) const override
SUnit * Clone(SUnit *Old)
Clone - Creates a clone of the specified SUnit.
void dumpSchedule() const
virtual void computeOperandLatency(SDNode *Def, SDNode *Use, unsigned OpIdx, SDep &dep) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
A Use represents the edge between a Value definition and its users.
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
This is an optimization pass for GlobalISel generic memory operations.