LLVM 20.0.0git
SparcMCCodeEmitter.cpp
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1//===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the SparcMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
14#include "SparcMCExpr.h"
15#include "SparcMCTargetDesc.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCFixup.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCInstrInfo.h"
28#include "llvm/MC/MCSymbol.h"
32#include <cassert>
33#include <cstdint>
34
35using namespace llvm;
36
37#define DEBUG_TYPE "mccodeemitter"
38
39STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
40
41namespace {
42
43class SparcMCCodeEmitter : public MCCodeEmitter {
44 MCContext &Ctx;
45
46public:
47 SparcMCCodeEmitter(const MCInstrInfo &, MCContext &ctx)
48 : Ctx(ctx) {}
49 SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
50 SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete;
51 ~SparcMCCodeEmitter() override = default;
52
55 const MCSubtargetInfo &STI) const override;
56
57 // getBinaryCodeForInstr - TableGen'erated function for getting the
58 // binary encoding for an instruction.
59 uint64_t getBinaryCodeForInstr(const MCInst &MI,
61 const MCSubtargetInfo &STI) const;
62
63 /// getMachineOpValue - Return binary encoding of operand. If the machine
64 /// operand requires relocation, record the relocation and return zero.
65 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
67 const MCSubtargetInfo &STI) const;
68 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
70 const MCSubtargetInfo &STI) const;
71 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
73 const MCSubtargetInfo &STI) const;
74 unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
76 const MCSubtargetInfo &STI) const;
77 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
79 const MCSubtargetInfo &STI) const;
80 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
82 const MCSubtargetInfo &STI) const;
83};
84
85} // end anonymous namespace
86
87void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI,
90 const MCSubtargetInfo &STI) const {
91 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
93 Ctx.getAsmInfo()->isLittleEndian()
96
97 // Some instructions have phantom operands that only contribute a fixup entry.
98 unsigned SymOpNo = 0;
99 switch (MI.getOpcode()) {
100 default: break;
101 case SP::TLS_CALL: SymOpNo = 1; break;
102 case SP::GDOP_LDrr:
103 case SP::GDOP_LDXrr:
104 case SP::TLS_ADDrr:
105 case SP::TLS_LDrr:
106 case SP::TLS_LDXrr: SymOpNo = 3; break;
107 }
108 if (SymOpNo != 0) {
109 const MCOperand &MO = MI.getOperand(SymOpNo);
110 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
111 assert(op == 0 && "Unexpected operand value!");
112 (void)op; // suppress warning.
113 }
114
115 ++MCNumEmitted; // Keep track of the # of mi's emitted.
116}
117
118unsigned SparcMCCodeEmitter::
119getMachineOpValue(const MCInst &MI, const MCOperand &MO,
121 const MCSubtargetInfo &STI) const {
122 if (MO.isReg())
123 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
124
125 if (MO.isImm())
126 return MO.getImm();
127
128 assert(MO.isExpr());
129 const MCExpr *Expr = MO.getExpr();
130 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
131 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
132 Fixups.push_back(MCFixup::create(0, Expr, Kind));
133 return 0;
134 }
135
136 int64_t Res;
137 if (Expr->evaluateAsAbsolute(Res))
138 return Res;
139
140 llvm_unreachable("Unhandled expression!");
141 return 0;
142}
143
144unsigned
145SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
147 const MCSubtargetInfo &STI) const {
148 const MCOperand &MO = MI.getOperand(OpNo);
149
150 if (MO.isImm())
151 return MO.getImm();
152
153 assert(MO.isExpr() &&
154 "getSImm13OpValue expects only expressions or an immediate");
155
156 const MCExpr *Expr = MO.getExpr();
157
158 // Constant value, no fixup is needed
159 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
160 return CE->getValue();
161
163 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
164 Kind = MCFixupKind(SExpr->getFixupKind());
165 } else {
166 bool IsPic = Ctx.getObjectFileInfo()->isPositionIndependent();
168 : MCFixupKind(Sparc::fixup_sparc_13);
169 }
170
171 Fixups.push_back(MCFixup::create(0, Expr, Kind));
172 return 0;
173}
174
175unsigned SparcMCCodeEmitter::
176getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
178 const MCSubtargetInfo &STI) const {
179 const MCOperand &MO = MI.getOperand(OpNo);
180 const MCExpr *Expr = MO.getExpr();
181 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr);
182
183 if (MI.getOpcode() == SP::TLS_CALL) {
184 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
185 // encodeInstruction.
186#ifndef NDEBUG
187 // Verify that the callee is actually __tls_get_addr.
188 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
189 "Unexpected expression in TLS_CALL");
190 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
191 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
192 "Unexpected function for TLS_CALL");
193#endif
194 return 0;
195 }
196
198 Fixups.push_back(MCFixup::create(0, Expr, Kind));
199 return 0;
200}
201
202unsigned SparcMCCodeEmitter::
203getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
205 const MCSubtargetInfo &STI) const {
206 const MCOperand &MO = MI.getOperand(OpNo);
207 if (MO.isReg() || MO.isImm())
208 return getMachineOpValue(MI, MO, Fixups, STI);
209
210 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
212 return 0;
213}
214
215unsigned SparcMCCodeEmitter::
216getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
218 const MCSubtargetInfo &STI) const {
219 const MCOperand &MO = MI.getOperand(OpNo);
220 if (MO.isReg() || MO.isImm())
221 return getMachineOpValue(MI, MO, Fixups, STI);
222
223 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
225 return 0;
226}
227
228unsigned SparcMCCodeEmitter::
229getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
231 const MCSubtargetInfo &STI) const {
232 const MCOperand &MO = MI.getOperand(OpNo);
233 if (MO.isReg() || MO.isImm())
234 return getMachineOpValue(MI, MO, Fixups, STI);
235
236 Fixups.push_back(
238
239 return 0;
240}
241
242#include "SparcGenMCCodeEmitter.inc"
243
245 MCContext &Ctx) {
246 return new SparcMCCodeEmitter(MCII, Ctx);
247}
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
#define op(i)
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:166
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
Context object for machine code objects.
Definition: MCContext.h:83
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:39
ExprKind getKind() const
Definition: MCExpr.h:78
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:37
int64_t getImm() const
Definition: MCInst.h:81
bool isImm() const
Definition: MCInst.h:63
bool isReg() const
Definition: MCInst.h:62
MCRegister getReg() const
Returns the register number.
Definition: MCInst.h:70
const MCExpr * getExpr() const
Definition: MCInst.h:115
bool isExpr() const
Definition: MCInst.h:66
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
const MCSymbol & getSymbol() const
Definition: MCExpr.h:411
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:205
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: SparcMCExpr.h:90
Sparc::Fixups getFixupKind() const
getFixupKind - Get the fixup kind of this expression.
Definition: SparcMCExpr.h:93
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_sparc_br16
fixup_sparc_bpr - 16-bit fixup for bpr
@ fixup_sparc_got13
fixup_sparc_got13 - 13-bit fixup corresponding to got13(foo)
@ fixup_sparc_br19
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
@ fixup_sparc_13
fixup_sparc_13 - 13-bit fixup
@ fixup_sparc_br22
fixup_sparc_br22 - 22-bit PC relative relocation for branches
@ CE
Windows NT (Windows on ARM)
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:92
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)