LLVM 20.0.0git
MipsSERegisterInfo.h
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1//===-- MipsSERegisterInfo.h - Mips32/64 Register Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips32/64 implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEREGISTERINFO_H
15#define LLVM_LIB_TARGET_MIPS_MIPSSEREGISTERINFO_H
16
17#include "MipsRegisterInfo.h"
18
19namespace llvm {
20
22public:
24
25 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
26
27 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
28
29 const TargetRegisterClass *intRegClass(unsigned Size) const override;
30
31private:
32 void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
33 int FrameIndex, uint64_t StackSize,
34 int64_t SPOffset) const override;
35};
36
37} // end namespace llvm
38
39#endif
uint64_t Size
uint64_t IntrinsicInst * II
const TargetRegisterClass * intRegClass(unsigned Size) const override
Return GPR register class.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18