RISCVVSETVLIInfoAnalysis.cpp File Reference

#include "RISCVVSETVLIInfoAnalysis.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/LiveIntervals.h"

Go to the source code of this file.

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::RISCV

Functions
static VNInfo *	llvm::RISCV::getVNInfoFromReg (Register Reg, const MachineInstr &MI, const LiveIntervals *LIS)
	Given a virtual register Reg, return the corresponding VNInfo for it.
static unsigned	llvm::RISCV::getVLOpNum (const MachineInstr &MI)
static unsigned	llvm::RISCV::getSEWOpNum (const MachineInstr &MI)
static unsigned	llvm::RISCV::getVecPolicyOpNum (const MachineInstr &MI)
static std::optional< unsigned >	llvm::RISCV::getEEWForLoadStore (const MachineInstr &MI)
	Get the EEW for a load or store instruction.
static bool	llvm::RISCV::isMaskRegOp (const MachineInstr &MI)
	Return true if this is an operation on mask registers.
static bool	llvm::RISCV::hasUndefinedPassthru (const MachineInstr &MI)
	Return true if the inactive elements in the result are entirely undefined.
static bool	llvm::RISCV::isLMUL1OrSmaller (RISCVVType::VLMUL LMUL)
bool	llvm::RISCV::areCompatibleVTYPEs (uint64_t CurVType, uint64_t NewVType, const DemandedFields &Used)
	Return true if moving from CurVType to NewVType is indistinguishable from the perspective of an instruction (or set of instructions) which use only the Used subfields and properties.
DemandedFields	llvm::RISCV::getDemanded (const MachineInstr &MI, const RISCVSubtarget *ST)
	Return the fields and properties demanded by the provided instruction.
static unsigned	llvm::RISCV::computeVLMAX (unsigned VLEN, unsigned SEW, RISCVVType::VLMUL VLMul)