LLVM 19.0.0git
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1//===-- SPIRVAsmBackend.cpp - SPIR-V Assembler Backend ---------*- C++ -*--===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
11#include "llvm/MC/MCAssembler.h"
15using namespace llvm;
17namespace {
19class SPIRVAsmBackend : public MCAsmBackend {
21 SPIRVAsmBackend(llvm::endianness Endian) : MCAsmBackend(Endian) {}
23 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
25 uint64_t Value, bool IsResolved,
26 const MCSubtargetInfo *STI) const override {}
28 std::unique_ptr<MCObjectTargetWriter>
29 createObjectTargetWriter() const override {
31 }
33 // No instruction requires relaxation.
36 const MCAsmLayout &Layout) const override {
37 return false;
38 }
40 unsigned getNumFixupKinds() const override { return 1; }
42 bool mayNeedRelaxation(const MCInst &Inst,
43 const MCSubtargetInfo &STI) const override {
44 return false;
45 }
47 void relaxInstruction(MCInst &Inst,
48 const MCSubtargetInfo &STI) const override {}
51 const MCSubtargetInfo *STI) const override {
52 return false;
53 }
56} // end anonymous namespace
59 const MCSubtargetInfo &STI,
60 const MCRegisterInfo &MRI,
61 const MCTargetOptions &) {
62 return new SPIRVAsmBackend(llvm::endianness::little);
unsigned const MachineRegisterInfo * MRI
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
PowerPC TLS Dynamic Call Fixup
endianness Endian
raw_pwrite_stream & OS
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:43
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
Definition: MCAsmBackend.h:186
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
Definition: MCAsmBackend.h:163
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const =0
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:274
Generic base class for all target subtargets.
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::unique_ptr< MCObjectTargetWriter > createSPIRVObjectTargetWriter()
MCAsmBackend * createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: bit.h:70