LLVM 22.0.0git
SPIRVAsmBackend.cpp
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1//===-- SPIRVAsmBackend.cpp - SPIR-V Assembler Backend ---------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "llvm/MC/MCAssembler.h"
14
15using namespace llvm;
16
17namespace {
18
19class SPIRVAsmBackend : public MCAsmBackend {
20public:
21 SPIRVAsmBackend(llvm::endianness Endian) : MCAsmBackend(Endian) {}
22
23 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,
24 uint8_t *Data, uint64_t Value, bool IsResolved) override {}
25
26 std::unique_ptr<MCObjectTargetWriter>
27 createObjectTargetWriter() const override {
28 return std::make_unique<MCSPIRVObjectTargetWriter>();
29 }
30
31 bool writeNopData(raw_ostream &OS, uint64_t Count,
32 const MCSubtargetInfo *STI) const override {
33 return false;
34 }
35};
36
37} // end anonymous namespace
38
40 const MCSubtargetInfo &STI,
41 const MCRegisterInfo &MRI,
42 const MCTargetOptions &) {
43 return new SPIRVAsmBackend(llvm::endianness::little);
44}
unsigned const MachineRegisterInfo * MRI
#define T
Generic interface to target specific assembler backends.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
Definition InstrProf.h:137
FunctionAddr VTableAddr Count
Definition InstrProf.h:139
FunctionAddr VTableAddr uintptr_t uintptr_t Data
Definition InstrProf.h:189
MCAsmBackend * createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
endianness
Definition bit.h:71