LLVM 24.0.0git
XtensaMCCodeEmitter.cpp
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1//===-- XtensaMCCodeEmitter.cpp - Convert Xtensa Code to Machine Code -----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6// See https://llvm.org/LICENSE.txt for license information.
7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8//
9//===----------------------------------------------------------------------===//
10//
11// This file implements the XtensaMCCodeEmitter class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MCTargetDesc/XtensaFixupKinds.h"
16#include "MCTargetDesc/XtensaMCAsmInfo.h"
17#include "MCTargetDesc/XtensaMCTargetDesc.h"
18#include "llvm/MC/MCCodeEmitter.h"
19#include "llvm/MC/MCContext.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/MC/MCRegisterInfo.h"
24
25#define GET_INSTRMAP_INFO
26#include "XtensaGenInstrInfo.inc"
27#undef GET_INSTRMAP_INFO
28
29using namespace llvm;
30
31#define DEBUG_TYPE "mccodeemitter"
32
33namespace {
34class XtensaMCCodeEmitter : public MCCodeEmitter {
35 const MCInstrInfo &MCII;
36 MCContext &Ctx;
37 bool IsLittleEndian;
38
39public:
40 XtensaMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool isLE)
41 : MCII(mcii), Ctx(ctx), IsLittleEndian(isLE) {}
42
43 ~XtensaMCCodeEmitter() {}
44
45 // OVerride MCCodeEmitter.
46 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
47 SmallVectorImpl<MCFixup> &Fixups,
48 const MCSubtargetInfo &STI) const override;
49
50private:
51 // Automatically generated by TableGen.
52 uint64_t getBinaryCodeForInstr(const MCInst &MI,
53 SmallVectorImpl<MCFixup> &Fixups,
54 const MCSubtargetInfo &STI) const;
55
56 // Called by the TableGen code to get the binary encoding of operand
57 // MO in MI. Fixups is the list of fixups against MI.
58 uint32_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
59 SmallVectorImpl<MCFixup> &Fixups,
60 const MCSubtargetInfo &STI) const;
61
62 uint32_t getJumpTargetEncoding(const MCInst &MI, unsigned int OpNum,
63 SmallVectorImpl<MCFixup> &Fixups,
64 const MCSubtargetInfo &STI) const;
65
66 uint32_t getBranchTargetEncoding(const MCInst &MI, unsigned int OpNum,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const;
69
70 uint32_t getLoopTargetEncoding(const MCInst &MI, unsigned int OpNum,
71 SmallVectorImpl<MCFixup> &Fixups,
72 const MCSubtargetInfo &STI) const;
73
74 uint32_t getCallEncoding(const MCInst &MI, unsigned int OpNum,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
77
78 uint32_t getL32RTargetEncoding(const MCInst &MI, unsigned OpNum,
79 SmallVectorImpl<MCFixup> &Fixups,
80 const MCSubtargetInfo &STI) const;
81
82 uint32_t getMemRegEncoding(const MCInst &MI, unsigned OpNo,
83 SmallVectorImpl<MCFixup> &Fixups,
84 const MCSubtargetInfo &STI) const;
85
86 uint32_t getImm8OpValue(const MCInst &MI, unsigned OpNo,
87 SmallVectorImpl<MCFixup> &Fixups,
88 const MCSubtargetInfo &STI) const;
89
90 uint32_t getImm8_sh8OpValue(const MCInst &MI, unsigned OpNo,
91 SmallVectorImpl<MCFixup> &Fixups,
92 const MCSubtargetInfo &STI) const;
93
94 uint32_t getImm12OpValue(const MCInst &MI, unsigned OpNo,
95 SmallVectorImpl<MCFixup> &Fixups,
96 const MCSubtargetInfo &STI) const;
97
98 uint32_t getUimm4OpValue(const MCInst &MI, unsigned OpNo,
99 SmallVectorImpl<MCFixup> &Fixups,
100 const MCSubtargetInfo &STI) const;
101
102 uint32_t getUimm5OpValue(const MCInst &MI, unsigned OpNo,
103 SmallVectorImpl<MCFixup> &Fixups,
104 const MCSubtargetInfo &STI) const;
105
106 uint32_t getImm1_16OpValue(const MCInst &MI, unsigned OpNo,
107 SmallVectorImpl<MCFixup> &Fixups,
108 const MCSubtargetInfo &STI) const;
109
110 uint32_t getImm1n_15OpValue(const MCInst &MI, unsigned OpNo,
111 SmallVectorImpl<MCFixup> &Fixups,
112 const MCSubtargetInfo &STI) const;
113
114 uint32_t getImm32n_95OpValue(const MCInst &MI, unsigned OpNo,
115 SmallVectorImpl<MCFixup> &Fixups,
116 const MCSubtargetInfo &STI) const;
117
118 uint32_t getImm8n_7OpValue(const MCInst &MI, unsigned OpNo,
119 SmallVectorImpl<MCFixup> &Fixups,
120 const MCSubtargetInfo &STI) const;
121
122 uint32_t getImm64n_4nOpValue(const MCInst &MI, unsigned OpNo,
123 SmallVectorImpl<MCFixup> &Fixups,
124 const MCSubtargetInfo &STI) const;
125
126 uint32_t getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo,
127 SmallVectorImpl<MCFixup> &Fixups,
128 const MCSubtargetInfo &STI) const;
129
130 uint32_t getShimm1_31OpValue(const MCInst &MI, unsigned OpNo,
131 SmallVectorImpl<MCFixup> &Fixups,
132 const MCSubtargetInfo &STI) const;
133
134 uint32_t getB4constOpValue(const MCInst &MI, unsigned OpNo,
135 SmallVectorImpl<MCFixup> &Fixups,
136 const MCSubtargetInfo &STI) const;
137
138 uint32_t getB4constuOpValue(const MCInst &MI, unsigned OpNo,
139 SmallVectorImpl<MCFixup> &Fixups,
140 const MCSubtargetInfo &STI) const;
141
142 uint32_t getImm7_22OpValue(const MCInst &MI, unsigned OpNo,
143 SmallVectorImpl<MCFixup> &Fixups,
144 const MCSubtargetInfo &STI) const;
145
146 uint8_t getSelect_2OpValue(const MCInst &MI, unsigned OpNo,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI) const;
149
150 uint8_t getSelect_4OpValue(const MCInst &MI, unsigned OpNo,
151 SmallVectorImpl<MCFixup> &Fixups,
152 const MCSubtargetInfo &STI) const;
153
154 uint8_t getSelect_8OpValue(const MCInst &MI, unsigned OpNo,
155 SmallVectorImpl<MCFixup> &Fixups,
156 const MCSubtargetInfo &STI) const;
157
158 uint8_t getSelect_16OpValue(const MCInst &MI, unsigned OpNo,
159 SmallVectorImpl<MCFixup> &Fixups,
160 const MCSubtargetInfo &STI) const;
161
162 uint8_t getSelect_256OpValue(const MCInst &MI, unsigned OpNo,
163 SmallVectorImpl<MCFixup> &Fixups,
164 const MCSubtargetInfo &STI) const;
165
166 int8_t getOffset_16_16OpValue(const MCInst &MI, unsigned OpNo,
167 SmallVectorImpl<MCFixup> &Fixups,
168 const MCSubtargetInfo &STI) const;
169
170 int16_t getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo,
171 SmallVectorImpl<MCFixup> &Fixups,
172 const MCSubtargetInfo &STI) const;
173
174 int16_t getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo,
175 SmallVectorImpl<MCFixup> &Fixups,
176 const MCSubtargetInfo &STI) const;
177
178 int16_t getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo,
179 SmallVectorImpl<MCFixup> &Fixups,
180 const MCSubtargetInfo &STI) const;
181
182 uint8_t getOffset_128_2OpValue(const MCInst &MI, unsigned OpNo,
183 SmallVectorImpl<MCFixup> &Fixups,
184 const MCSubtargetInfo &STI) const;
185
186 uint8_t getOffset_128_1OpValue(const MCInst &MI, unsigned OpNo,
187 SmallVectorImpl<MCFixup> &Fixups,
188 const MCSubtargetInfo &STI) const;
189
190 int16_t getOffset_64_16OpValue(const MCInst &MI, unsigned OpNo,
191 SmallVectorImpl<MCFixup> &Fixups,
192 const MCSubtargetInfo &STI) const;
193};
194} // namespace
195
196MCCodeEmitter *llvm::createXtensaMCCodeEmitter(const MCInstrInfo &MCII,
197 MCContext &Ctx) {
198 return new XtensaMCCodeEmitter(MCII, Ctx, true);
199}
200
201static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
202 const MCExpr *Value, uint16_t Kind) {
203 bool PCRel = false;
204 switch (Kind) {
205 case Xtensa::fixup_xtensa_branch_6:
206 case Xtensa::fixup_xtensa_branch_8:
207 case Xtensa::fixup_xtensa_branch_12:
208 case Xtensa::fixup_xtensa_jump_18:
209 case Xtensa::fixup_xtensa_call_18:
210 case Xtensa::fixup_xtensa_l32r_16:
211 case Xtensa::fixup_xtensa_loop_8:
212 PCRel = true;
213 }
214 Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
215}
216
217void XtensaMCCodeEmitter::encodeInstruction(const MCInst &MI,
218 SmallVectorImpl<char> &CB,
219 SmallVectorImpl<MCFixup> &Fixups,
220 const MCSubtargetInfo &STI) const {
221 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
222 unsigned Size = MCII.get(MI.getOpcode()).getSize();
223
224 if (IsLittleEndian) {
225 // Little-endian insertion of Size bytes.
226 unsigned ShiftValue = 0;
227 for (unsigned I = 0; I != Size; ++I) {
228 CB.push_back(char(Bits >> ShiftValue));
229 ShiftValue += 8;
230 }
231 } else {
232 // TODO Big-endian insertion of Size bytes.
233 report_fatal_error("Big-endian mode currently is not supported!");
234 }
235}
236
237uint32_t
238XtensaMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
239 SmallVectorImpl<MCFixup> &Fixups,
240 const MCSubtargetInfo &STI) const {
241 if (MO.isReg())
242 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
243 if (MO.isImm()) {
244 uint32_t Res = static_cast<uint32_t>(MO.getImm());
245 return Res;
246 }
247
248 report_fatal_error("Unhandled expression!");
249 return 0;
250}
251
252uint32_t
253XtensaMCCodeEmitter::getJumpTargetEncoding(const MCInst &MI, unsigned int OpNum,
254 SmallVectorImpl<MCFixup> &Fixups,
255 const MCSubtargetInfo &STI) const {
256 const MCOperand &MO = MI.getOperand(OpNum);
257
258 if (MO.isImm())
259 return MO.getImm();
260
261 const MCExpr *Expr = MO.getExpr();
262 addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_jump_18);
263 return 0;
264}
265
266uint32_t XtensaMCCodeEmitter::getBranchTargetEncoding(
267 const MCInst &MI, unsigned int OpNum, SmallVectorImpl<MCFixup> &Fixups,
268 const MCSubtargetInfo &STI) const {
269 const MCOperand &MO = MI.getOperand(OpNum);
270 if (MO.isImm())
271 return static_cast<uint32_t>(MO.getImm());
272
273 const MCExpr *Expr = MO.getExpr();
274 switch (MI.getOpcode()) {
275 case Xtensa::BEQZ:
276 case Xtensa::BGEZ:
277 case Xtensa::BLTZ:
278 case Xtensa::BNEZ:
279 addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_branch_12);
280 return 0;
281 case Xtensa::BEQZ_N:
282 case Xtensa::BNEZ_N:
283 addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_branch_6);
284 return 0;
285 default:
286 addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_branch_8);
287 return 0;
288 }
289}
290
291uint32_t
292XtensaMCCodeEmitter::getLoopTargetEncoding(const MCInst &MI, unsigned int OpNum,
293 SmallVectorImpl<MCFixup> &Fixups,
294 const MCSubtargetInfo &STI) const {
295 const MCOperand &MO = MI.getOperand(OpNum);
296 if (MO.isImm())
297 return static_cast<uint32_t>(MO.getImm());
298
299 assert((MO.isExpr()) && "Unexpected operand value!");
300
301 const MCExpr *Expr = MO.getExpr();
302
303 addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_loop_8);
304 return 0;
305}
306
307uint32_t
308XtensaMCCodeEmitter::getCallEncoding(const MCInst &MI, unsigned int OpNum,
309 SmallVectorImpl<MCFixup> &Fixups,
310 const MCSubtargetInfo &STI) const {
311 const MCOperand &MO = MI.getOperand(OpNum);
312 if (MO.isImm()) {
313 int32_t Res = MO.getImm();
314 if (Res & 0x3) {
315 llvm_unreachable("Unexpected operand value!");
316 }
317 Res >>= 2;
318 return Res;
319 }
320
321 assert((MO.isExpr()) && "Unexpected operand value!");
322 const MCExpr *Expr = MO.getExpr();
323 addFixup(Fixups, 0, Expr, Xtensa::fixup_xtensa_call_18);
324 return 0;
325}
326
327uint32_t
328XtensaMCCodeEmitter::getL32RTargetEncoding(const MCInst &MI, unsigned OpNum,
329 SmallVectorImpl<MCFixup> &Fixups,
330 const MCSubtargetInfo &STI) const {
331 const MCOperand &MO = MI.getOperand(OpNum);
332 if (MO.isImm()) {
333 int32_t Res = MO.getImm();
334 // We don't check first 2 bits, because in these bits we could store first 2
335 // bits of instruction address
336 Res >>= 2;
337 return Res;
338 }
339
340 assert((MO.isExpr()) && "Unexpected operand value!");
341
342 addFixup(Fixups, 0, MO.getExpr(), Xtensa::fixup_xtensa_l32r_16);
343 return 0;
344}
345
346uint32_t
347XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo,
348 SmallVectorImpl<MCFixup> &Fixups,
349 const MCSubtargetInfo &STI) const {
350 assert(MI.getOperand(OpNo + 1).isImm());
351
352 uint32_t Res = static_cast<uint32_t>(MI.getOperand(OpNo + 1).getImm());
353
354 switch (MI.getOpcode()) {
355 case Xtensa::S16I:
356 case Xtensa::L16SI:
357 case Xtensa::L16UI:
358 if (Res & 0x1) {
359 report_fatal_error("Unexpected operand value!");
360 }
361 Res >>= 1;
362 break;
363 case Xtensa::S32I:
364 case Xtensa::L32I:
365 case Xtensa::S32I_N:
366 case Xtensa::L32I_N:
367 case Xtensa::SSI:
368 case Xtensa::SSIP:
369 case Xtensa::LSI:
370 case Xtensa::LSIP:
371 case Xtensa::S32C1I:
372 if (Res & 0x3) {
373 report_fatal_error("Unexpected operand value!");
374 }
375 Res >>= 2;
376 break;
377 }
378
379 switch (MI.getOpcode()) {
380 case Xtensa::S32I_N:
381 case Xtensa::L32I_N:
382 assert((isUInt<4>(Res)) && "Unexpected operand value!");
383 break;
384 default:
385 assert((isUInt<8>(Res)) && "Unexpected operand value!");
386 break;
387 }
388
389 uint32_t OffBits = Res << 4;
390 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
391
392 return ((OffBits & 0xFF0) | RegBits);
393}
394
395uint32_t XtensaMCCodeEmitter::getImm8OpValue(const MCInst &MI, unsigned OpNo,
396 SmallVectorImpl<MCFixup> &Fixups,
397 const MCSubtargetInfo &STI) const {
398 const MCOperand &MO = MI.getOperand(OpNo);
399 int32_t Res = MO.getImm();
400
401 assert(((Res >= -128) && (Res <= 127)) && "Unexpected operand value!");
402
403 return (Res & 0xff);
404}
405
406uint32_t
407XtensaMCCodeEmitter::getImm8_sh8OpValue(const MCInst &MI, unsigned OpNo,
408 SmallVectorImpl<MCFixup> &Fixups,
409 const MCSubtargetInfo &STI) const {
410 const MCOperand &MO = MI.getOperand(OpNo);
411 int32_t Res = MO.getImm();
412
413 assert(((Res >= -32768) && (Res <= 32512) && ((Res & 0xff) == 0)) &&
414 "Unexpected operand value!");
415
416 return (Res & 0xffff);
417}
418
419uint32_t
420XtensaMCCodeEmitter::getImm12OpValue(const MCInst &MI, unsigned OpNo,
421 SmallVectorImpl<MCFixup> &Fixups,
422 const MCSubtargetInfo &STI) const {
423 const MCOperand &MO = MI.getOperand(OpNo);
424 int32_t Res = MO.getImm();
425
426 assert(((Res >= -2048) && (Res <= 2047)) && "Unexpected operand value!");
427
428 return (Res & 0xfff);
429}
430
431uint32_t
432XtensaMCCodeEmitter::getUimm4OpValue(const MCInst &MI, unsigned OpNo,
433 SmallVectorImpl<MCFixup> &Fixups,
434 const MCSubtargetInfo &STI) const {
435 const MCOperand &MO = MI.getOperand(OpNo);
436 uint32_t Res = static_cast<uint32_t>(MO.getImm());
437
438 assert((Res <= 15) && "Unexpected operand value!");
439
440 return Res & 0xf;
441}
442
443uint32_t
444XtensaMCCodeEmitter::getUimm5OpValue(const MCInst &MI, unsigned OpNo,
445 SmallVectorImpl<MCFixup> &Fixups,
446 const MCSubtargetInfo &STI) const {
447 const MCOperand &MO = MI.getOperand(OpNo);
448 uint32_t Res = static_cast<uint32_t>(MO.getImm());
449
450 assert((Res <= 31) && "Unexpected operand value!");
451
452 return (Res & 0x1f);
453}
454
455uint32_t
456XtensaMCCodeEmitter::getShimm1_31OpValue(const MCInst &MI, unsigned OpNo,
457 SmallVectorImpl<MCFixup> &Fixups,
458 const MCSubtargetInfo &STI) const {
459 const MCOperand &MO = MI.getOperand(OpNo);
460 uint32_t Res = static_cast<uint32_t>(MO.getImm());
461
462 assert(((Res >= 1) && (Res <= 31)) && "Unexpected operand value!");
463
464 return ((32 - Res) & 0x1f);
465}
466
467uint32_t
468XtensaMCCodeEmitter::getImm1_16OpValue(const MCInst &MI, unsigned OpNo,
469 SmallVectorImpl<MCFixup> &Fixups,
470 const MCSubtargetInfo &STI) const {
471 const MCOperand &MO = MI.getOperand(OpNo);
472 uint32_t Res = static_cast<uint32_t>(MO.getImm());
473
474 assert(((Res >= 1) && (Res <= 16)) && "Unexpected operand value!");
475
476 return (Res - 1);
477}
478
479uint32_t
480XtensaMCCodeEmitter::getImm1n_15OpValue(const MCInst &MI, unsigned OpNo,
481 SmallVectorImpl<MCFixup> &Fixups,
482 const MCSubtargetInfo &STI) const {
483 const MCOperand &MO = MI.getOperand(OpNo);
484 int32_t Res = static_cast<int32_t>(MO.getImm());
485
486 assert(((Res >= -1) && (Res <= 15) && (Res != 0)) &&
487 "Unexpected operand value!");
488
489 if (Res < 0)
490 Res = 0;
491
492 return Res;
493}
494
495uint32_t
496XtensaMCCodeEmitter::getImm32n_95OpValue(const MCInst &MI, unsigned OpNo,
497 SmallVectorImpl<MCFixup> &Fixups,
498 const MCSubtargetInfo &STI) const {
499 const MCOperand &MO = MI.getOperand(OpNo);
500 int32_t Res = static_cast<int32_t>(MO.getImm());
501
502 assert(((Res >= -32) && (Res <= 95)) && "Unexpected operand value!");
503
504 return Res;
505}
506
507uint32_t
508XtensaMCCodeEmitter::getImm8n_7OpValue(const MCInst &MI, unsigned OpNo,
509 SmallVectorImpl<MCFixup> &Fixups,
510 const MCSubtargetInfo &STI) const {
511 const MCOperand &MO = MI.getOperand(OpNo);
512 int32_t Res = static_cast<int32_t>(MO.getImm());
513
514 assert(((Res >= -8) && (Res <= 7)) && "Unexpected operand value!");
515
516 if (Res < 0)
517 return Res + 16;
518
519 return Res;
520}
521
522uint32_t
523XtensaMCCodeEmitter::getImm64n_4nOpValue(const MCInst &MI, unsigned OpNo,
524 SmallVectorImpl<MCFixup> &Fixups,
525 const MCSubtargetInfo &STI) const {
526 const MCOperand &MO = MI.getOperand(OpNo);
527 int32_t Res = static_cast<int32_t>(MO.getImm());
528
529 assert(((Res >= -64) && (Res <= -4) && ((Res & 0x3) == 0)) &&
530 "Unexpected operand value!");
531
532 return Res & 0x3f;
533}
534
535uint32_t
536XtensaMCCodeEmitter::getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo,
537 SmallVectorImpl<MCFixup> &Fixups,
538 const MCSubtargetInfo &STI) const {
539 const MCOperand &MO = MI.getOperand(OpNo);
540 uint32_t res = static_cast<uint32_t>(MO.getImm());
541
542 assert(((res & 0x7) == 0) && "Unexpected operand value!");
543
544 return res;
545}
546
547uint32_t
548XtensaMCCodeEmitter::getB4constOpValue(const MCInst &MI, unsigned OpNo,
549 SmallVectorImpl<MCFixup> &Fixups,
550 const MCSubtargetInfo &STI) const {
551 const MCOperand &MO = MI.getOperand(OpNo);
552 uint32_t Res = static_cast<uint32_t>(MO.getImm());
553
554 switch (Res) {
555 case 0xffffffff:
556 Res = 0;
557 break;
558 case 1:
559 case 2:
560 case 3:
561 case 4:
562 case 5:
563 case 6:
564 case 7:
565 case 8:
566 break;
567 case 10:
568 Res = 9;
569 break;
570 case 12:
571 Res = 10;
572 break;
573 case 16:
574 Res = 11;
575 break;
576 case 32:
577 Res = 12;
578 break;
579 case 64:
580 Res = 13;
581 break;
582 case 128:
583 Res = 14;
584 break;
585 case 256:
586 Res = 15;
587 break;
588 default:
589 llvm_unreachable("Unexpected operand value!");
590 }
591
592 return Res;
593}
594
595uint32_t
596XtensaMCCodeEmitter::getB4constuOpValue(const MCInst &MI, unsigned OpNo,
597 SmallVectorImpl<MCFixup> &Fixups,
598 const MCSubtargetInfo &STI) const {
599 const MCOperand &MO = MI.getOperand(OpNo);
600 uint32_t Res = static_cast<uint32_t>(MO.getImm());
601
602 switch (Res) {
603 case 32768:
604 Res = 0;
605 break;
606 case 65536:
607 Res = 1;
608 break;
609 case 2:
610 case 3:
611 case 4:
612 case 5:
613 case 6:
614 case 7:
615 case 8:
616 break;
617 case 10:
618 Res = 9;
619 break;
620 case 12:
621 Res = 10;
622 break;
623 case 16:
624 Res = 11;
625 break;
626 case 32:
627 Res = 12;
628 break;
629 case 64:
630 Res = 13;
631 break;
632 case 128:
633 Res = 14;
634 break;
635 case 256:
636 Res = 15;
637 break;
638 default:
639 llvm_unreachable("Unexpected operand value!");
640 }
641
642 return Res;
643}
644
645uint32_t
646XtensaMCCodeEmitter::getImm7_22OpValue(const MCInst &MI, unsigned OpNo,
647 SmallVectorImpl<MCFixup> &Fixups,
648 const MCSubtargetInfo &STI) const {
649 const MCOperand &MO = MI.getOperand(OpNo);
650 uint32_t res = static_cast<uint32_t>(MO.getImm());
651
652 res -= 7;
653 assert(((res & 0xf) == res) && "Unexpected operand value!");
654
655 return res;
656}
657
658uint8_t
659XtensaMCCodeEmitter::getSelect_2OpValue(const MCInst &MI, unsigned OpNo,
660 SmallVectorImpl<MCFixup> &Fixups,
661 const MCSubtargetInfo &STI) const {
662 const MCOperand &MO = MI.getOperand(OpNo);
663 uint8_t Res = static_cast<uint8_t>(MO.getImm());
664
665 assert(((Res >= 0) && (Res <= 1)) && "Unexpected operand value!");
666
667 return Res;
668}
669
670uint8_t
671XtensaMCCodeEmitter::getSelect_4OpValue(const MCInst &MI, unsigned OpNo,
672 SmallVectorImpl<MCFixup> &Fixups,
673 const MCSubtargetInfo &STI) const {
674 const MCOperand &MO = MI.getOperand(OpNo);
675 uint8_t Res = static_cast<uint8_t>(MO.getImm());
676
677 assert(((Res >= 0) && (Res <= 3)) && "Unexpected operand value!");
678
679 return Res;
680}
681
682uint8_t
683XtensaMCCodeEmitter::getSelect_8OpValue(const MCInst &MI, unsigned OpNo,
684 SmallVectorImpl<MCFixup> &Fixups,
685 const MCSubtargetInfo &STI) const {
686 const MCOperand &MO = MI.getOperand(OpNo);
687 uint8_t Res = static_cast<uint8_t>(MO.getImm());
688
689 assert(((Res >= 0) && (Res <= 7)) && "Unexpected operand value!");
690
691 return Res;
692}
693
694uint8_t
695XtensaMCCodeEmitter::getSelect_16OpValue(const MCInst &MI, unsigned OpNo,
696 SmallVectorImpl<MCFixup> &Fixups,
697 const MCSubtargetInfo &STI) const {
698 const MCOperand &MO = MI.getOperand(OpNo);
699 uint8_t Res = static_cast<uint8_t>(MO.getImm());
700
701 assert(((Res >= 0) && (Res <= 15)) && "Unexpected operand value!");
702
703 return Res;
704}
705
706uint8_t
707XtensaMCCodeEmitter::getSelect_256OpValue(const MCInst &MI, unsigned OpNo,
708 SmallVectorImpl<MCFixup> &Fixups,
709 const MCSubtargetInfo &STI) const {
710 const MCOperand &MO = MI.getOperand(OpNo);
711 uint8_t Res = static_cast<uint8_t>(MO.getImm());
712
713 assert(((Res >= 0) && (Res <= 255)) && "Unexpected operand value!");
714
715 return Res;
716}
717#include "XtensaGenMCCodeEmitter.inc"
718
719int8_t
720XtensaMCCodeEmitter::getOffset_16_16OpValue(const MCInst &MI, unsigned OpNo,
721 SmallVectorImpl<MCFixup> &Fixups,
722 const MCSubtargetInfo &STI) const {
723 const MCOperand &MO = MI.getOperand(OpNo);
724 int8_t Res = static_cast<int8_t>(MO.getImm());
725
726 assert(((Res >= -128) && (Res <= 112) && ((Res & 0xf) == 0)) &&
727 "Unexpected operand value!");
728
729 return Res / 16;
730}
731
732int16_t
733XtensaMCCodeEmitter::getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo,
734 SmallVectorImpl<MCFixup> &Fixups,
735 const MCSubtargetInfo &STI) const {
736 const MCOperand &MO = MI.getOperand(OpNo);
737 int16_t Res = static_cast<int16_t>(MO.getImm());
738
739 assert(((Res >= -1024) && (Res <= 1016) && ((Res & 0x7) == 0)) &&
740 "Unexpected operand value!");
741
742 return Res / 8;
743}
744
745int16_t
746XtensaMCCodeEmitter::getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo,
747 SmallVectorImpl<MCFixup> &Fixups,
748 const MCSubtargetInfo &STI) const {
749 const MCOperand &MO = MI.getOperand(OpNo);
750 int16_t Res = static_cast<int16_t>(MO.getImm());
751
752 assert(((Res >= -2048) && (Res <= 2032) && ((Res & 0xf) == 0)) &&
753 "Unexpected operand value!");
754
755 return Res / 16;
756}
757
758int16_t
759XtensaMCCodeEmitter::getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo,
760 SmallVectorImpl<MCFixup> &Fixups,
761 const MCSubtargetInfo &STI) const {
762 const MCOperand &MO = MI.getOperand(OpNo);
763 int16_t Res = static_cast<int16_t>(MO.getImm());
764
765 assert(((Res >= -512) && (Res <= 508) && ((Res & 0x3) == 0)) &&
766 "Unexpected operand value!");
767
768 return Res / 4;
769}
770
771uint8_t
772XtensaMCCodeEmitter::getOffset_128_2OpValue(const MCInst &MI, unsigned OpNo,
773 SmallVectorImpl<MCFixup> &Fixups,
774 const MCSubtargetInfo &STI) const {
775 const MCOperand &MO = MI.getOperand(OpNo);
776 uint8_t Res = static_cast<uint8_t>(MO.getImm());
777
778 assert(((Res >= 0) && (Res <= 254) && ((Res & 0x1) == 0)) &&
779 "Unexpected operand value!");
780
781 return Res / 2;
782}
783
784uint8_t
785XtensaMCCodeEmitter::getOffset_128_1OpValue(const MCInst &MI, unsigned OpNo,
786 SmallVectorImpl<MCFixup> &Fixups,
787 const MCSubtargetInfo &STI) const {
788 const MCOperand &MO = MI.getOperand(OpNo);
789 uint8_t Res = static_cast<uint8_t>(MO.getImm());
790
791 assert(((Res >= 0) && (Res <= 127)) && "Unexpected operand value!");
792
793 return Res;
794}
795
796int16_t
797XtensaMCCodeEmitter::getOffset_64_16OpValue(const MCInst &MI, unsigned OpNo,
798 SmallVectorImpl<MCFixup> &Fixups,
799 const MCSubtargetInfo &STI) const {
800 const MCOperand &MO = MI.getOperand(OpNo);
801 int16_t Res = static_cast<int16_t>(MO.getImm());
802
803 assert(((Res >= -512) && (Res <= 496) && ((Res & 0xf) == 0)) &&
804 "Unexpected operand value!");
805
806 return Res / 16;
807}
addFixup
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind, bool PCRel=false)
Definition AArch64MCCodeEmitter.cpp:225
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
uint64_t
unsigned uint64_t
Definition AMDGPUDisassembler.cpp:535
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:855
I
#define I(x, y, z)
Definition MD5.cpp:57
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition MCCodeEmitter.h:22
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition MCContext.h:411
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition MCExpr.h:34
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)
Consider bit fields if we need more flags.
Definition MCFixup.h:86
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition MCInstrDesc.h:609
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition MCInstrInfo.h:89
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
llvm::MCOperand::getImm
int64_t getImm() const
Definition MCInst.h:84
llvm::MCOperand::isImm
bool isImm() const
Definition MCInst.h:66
llvm::MCOperand::isReg
bool isReg() const
Definition MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition MCInst.h:118
llvm::MCOperand::isExpr
bool isExpr() const
Definition MCInst.h:69
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister Reg) const
Returns the encoding for Reg.
Definition MCRegisterInfo.h:605
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:141
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition SmallVector.h:592
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:423
llvm::Value
LLVM Value Representation.
Definition Value.h:75
uint16_t
uint32_t
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::getImm
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:1173
llvm::report_fatal_error
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:163
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190
llvm::addFixup
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)
Definition AVRMCCodeEmitter.cpp:38
llvm::createXtensaMCCodeEmitter
MCCodeEmitter * createXtensaMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition XtensaMCCodeEmitter.cpp:196
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