25#define GET_INSTRMAP_INFO
26#include "XtensaGenInstrInfo.inc"
27#undef GET_INSTRMAP_INFO
31#define DEBUG_TYPE "mccodeemitter"
41 : MCII(mcii), Ctx(ctx), IsLittleEndian(isLE) {}
43 ~XtensaMCCodeEmitter() {}
122 return new XtensaMCCodeEmitter(MCII, Ctx,
true);
128 uint64_t Bits = getBinaryCodeForInstr(
MI, Fixups, STI);
129 unsigned Size = MCII.get(
MI.getOpcode()).getSize();
131 if (IsLittleEndian) {
133 unsigned ShiftValue = 0;
134 for (
unsigned I = 0;
I !=
Size; ++
I) {
135 OS << uint8_t(Bits >> ShiftValue);
149 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
160XtensaMCCodeEmitter::getJumpTargetEncoding(
const MCInst &
MI,
unsigned int OpNum,
174uint32_t XtensaMCCodeEmitter::getBranchTargetEncoding(
182 switch (
MI.getOpcode()) {
198XtensaMCCodeEmitter::getCallEncoding(
const MCInst &
MI,
unsigned int OpNum,
203 int32_t Res = MO.
getImm();
219XtensaMCCodeEmitter::getL32RTargetEncoding(
const MCInst &
MI,
unsigned OpNum,
224 int32_t Res = MO.
getImm();
239XtensaMCCodeEmitter::getMemRegEncoding(
const MCInst &
MI,
unsigned OpNo,
242 assert(
MI.getOperand(OpNo + 1).isImm());
246 switch (
MI.getOpcode()) {
264 assert((isUInt<8>(Res)) &&
"Unexpected operand value!");
267 uint32_t RegBits = getMachineOpValue(
MI,
MI.getOperand(OpNo), Fixups, STI);
269 return ((OffBits & 0xFF0) | RegBits);
272uint32_t XtensaMCCodeEmitter::getImm8OpValue(
const MCInst &
MI,
unsigned OpNo,
276 int32_t Res = MO.
getImm();
278 assert(((Res >= -128) && (Res <= 127)) &&
"Unexpected operand value!");
284XtensaMCCodeEmitter::getImm8_sh8OpValue(
const MCInst &
MI,
unsigned OpNo,
288 int32_t Res = MO.
getImm();
290 assert(((Res >= -32768) && (Res <= 32512) && ((Res & 0xff) == 0)) &&
291 "Unexpected operand value!");
293 return (Res & 0xffff);
297XtensaMCCodeEmitter::getImm12OpValue(
const MCInst &
MI,
unsigned OpNo,
301 int32_t Res = MO.
getImm();
303 assert(((Res >= -2048) && (Res <= 2047)) &&
"Unexpected operand value!");
305 return (Res & 0xfff);
309XtensaMCCodeEmitter::getUimm4OpValue(
const MCInst &
MI,
unsigned OpNo,
315 assert((Res <= 15) &&
"Unexpected operand value!");
321XtensaMCCodeEmitter::getUimm5OpValue(
const MCInst &
MI,
unsigned OpNo,
327 assert((Res <= 31) &&
"Unexpected operand value!");
333XtensaMCCodeEmitter::getShimm1_31OpValue(
const MCInst &
MI,
unsigned OpNo,
339 assert(((Res >= 1) && (Res <= 31)) &&
"Unexpected operand value!");
341 return ((32 - Res) & 0x1f);
345XtensaMCCodeEmitter::getImm1_16OpValue(
const MCInst &
MI,
unsigned OpNo,
351 assert(((Res >= 1) && (Res <= 16)) &&
"Unexpected operand value!");
357XtensaMCCodeEmitter::getB4constOpValue(
const MCInst &
MI,
unsigned OpNo,
405XtensaMCCodeEmitter::getB4constuOpValue(
const MCInst &
MI,
unsigned OpNo,
453#include "XtensaGenMCCodeEmitter.inc"
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
Generic base class for all target subtargets.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCCodeEmitter * createXtensaMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)