25#define DEBUG_TYPE "instcombine"
29 cl::desc(
"Verify that computeKnownBits() and "
30 "SimplifyDemandedBits() are consistent"),
34 "instcombine-simplify-vector-elts-depth",
36 "Depth limit when simplifying vector instructions and their operands"),
43 const APInt &Demanded) {
45 assert(OpNo < I->getNumOperands() &&
"Operand index too large");
54 if (
C->isSubsetOf(Demanded))
58 I->setOperand(OpNo, ConstantInt::get(
Op->getType(), *
C & Demanded));
70 const APInt &DemandedMask,
73 assert(
I->getOpcode() == Instruction::LShr &&
74 "Only lshr instruction supported");
78 if (!
match(
I->getOperand(0),
88 if (DemandedBitWidth > ShlAmt)
92 if (
Upper->getType()->getScalarSizeInBits() < ShlAmt + DemandedBitWidth)
99 Value *ShrAmt =
I->getOperand(1);
104 if (~KnownShrBits.
Zero != ShlAmt)
118 if (
unsigned BitWidth = Ty->getScalarSizeInBits())
121 return DL.getPointerTypeSizeInBits(Ty);
130 SQ.getWithInstruction(&Inst));
131 if (!V)
return false;
132 if (V == &Inst)
return true;
148 const APInt &DemandedMask,
152 Use &U =
I->getOperandUse(OpNo);
160 if (DemandedMask.
isZero()) {
185 if (!NewVal)
return false;
217 const APInt &DemandedMask,
221 assert(
I !=
nullptr &&
"Null pointer of Value???");
224 Type *VTy =
I->getType();
228 "Value *V, DemandedMask and Known must have same BitWidth");
234 auto disableWrapFlagsBasedOnUnusedHighBits = [](
Instruction *
I,
240 I->setHasNoSignedWrap(
false);
241 I->setHasNoUnsignedWrap(
false);
248 auto simplifyOperandsBasedOnUnusedHighBits = [&](
APInt &DemandedFromOps) {
257 disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
263 switch (
I->getOpcode()) {
267 case Instruction::And: {
285 return I->getOperand(0);
287 return I->getOperand(1);
295 case Instruction::Or: {
301 I->dropPoisonGeneratingFlags();
316 return I->getOperand(0);
318 return I->getOperand(1);
327 RHSCache(
I->getOperand(1), RHSKnown);
336 case Instruction::Xor: {
341 if (DemandedMask == 1 &&
348 return Builder.CreateUnaryIntrinsic(Intrinsic::ctpop,
Xor);
362 return I->getOperand(0);
364 return I->getOperand(1);
371 BinaryOperator::CreateOr(
I->getOperand(0),
I->getOperand(1));
385 ~RHSKnown.
One & DemandedMask);
395 if ((*
C | ~DemandedMask).isAllOnes()) {
411 if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
414 (LHSKnown.One & RHSKnown.
One & DemandedMask) != 0) {
415 APInt NewMask = ~(LHSKnown.One & RHSKnown.
One & DemandedMask);
418 Instruction *NewAnd = BinaryOperator::CreateAnd(
I->getOperand(0), AndC);
422 Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
428 case Instruction::Select: {
438 auto CanonicalizeSelectConstant = [](
Instruction *
I,
unsigned OpNo,
439 const APInt &DemandedMask) {
459 if ((*CmpC & DemandedMask) == (*SelC & DemandedMask)) {
460 I->setOperand(OpNo, ConstantInt::get(
I->getType(), *CmpC));
465 if (CanonicalizeSelectConstant(
I, 1, DemandedMask) ||
466 CanonicalizeSelectConstant(
I, 2, DemandedMask))
477 case Instruction::Trunc: {
491 return Builder.CreateLShr(Trunc,
C->getZExtValue());
496 case Instruction::ZExt: {
497 unsigned SrcBitWidth =
I->getOperand(0)->getType()->getScalarSizeInBits();
505 I->dropPoisonGeneratingFlags();
509 if (
I->getOpcode() == Instruction::ZExt &&
I->hasNonNeg() &&
516 case Instruction::SExt: {
518 unsigned SrcBitWidth =
I->getOperand(0)->getType()->getScalarSizeInBits();
520 APInt InputDemandedBits = DemandedMask.
trunc(SrcBitWidth);
525 InputDemandedBits.
setBit(SrcBitWidth-1);
546 case Instruction::Add: {
547 if ((DemandedMask & 1) == 0) {
553 X->getType()->isIntOrIntVectorTy(1) &&
X->getType() ==
Y->getType()) {
563 return Builder.CreateSExt(AndNot, VTy);
568 X->getType()->isIntOrIntVectorTy(1) &&
X->getType() ==
Y->getType() &&
569 (
I->getOperand(0)->hasOneUse() ||
I->getOperand(1)->hasOneUse())) {
590 return disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
596 APInt DemandedFromLHS = DemandedFromOps;
600 return disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
605 return I->getOperand(0);
606 if (DemandedFromOps.
isSubsetOf(LHSKnown.Zero))
607 return I->getOperand(1);
616 return Builder.CreateXor(
I->getOperand(0), ConstantInt::get(VTy, *
C));
626 case Instruction::Sub: {
633 return disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
639 APInt DemandedFromLHS = DemandedFromOps;
643 return disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
648 return I->getOperand(0);
651 if (DemandedFromOps.
isOne() && DemandedFromOps.
isSubsetOf(LHSKnown.Zero))
652 return I->getOperand(1);
660 return Builder.CreateNot(
I->getOperand(1));
669 case Instruction::Mul: {
670 APInt DemandedFromOps;
671 if (simplifyOperandsBasedOnUnusedHighBits(DemandedFromOps))
681 Constant *ShiftC = ConstantInt::get(VTy, CTZ);
682 Instruction *Shl = BinaryOperator::CreateShl(
I->getOperand(0), ShiftC);
689 if (
I->getOperand(0) ==
I->getOperand(1) && DemandedMask.
ult(4)) {
690 Constant *One = ConstantInt::get(VTy, 1);
691 Instruction *And1 = BinaryOperator::CreateAnd(
I->getOperand(0), One);
698 case Instruction::Shl: {
705 DemandedMask, Known))
709 if (
I->hasOneUse()) {
711 if (Inst && Inst->getOpcode() == BinaryOperator::Or) {
713 auto [IID, FShiftArgs] = *Opt;
714 if ((IID == Intrinsic::fshl || IID == Intrinsic::fshr) &&
715 FShiftArgs[0] == FShiftArgs[1]) {
727 if (
I->hasNoSignedWrap()) {
731 if (SignBits > ShiftAmt && SignBits - ShiftAmt >= NumHiDemandedBits)
732 return I->getOperand(0);
742 Constant *LeftShiftAmtC = ConstantInt::get(VTy, ShiftAmt);
746 LeftShiftAmtC,
DL) ==
C) {
747 Instruction *Lshr = BinaryOperator::CreateLShr(NewC,
X);
753 APInt DemandedMaskIn(DemandedMask.
lshr(ShiftAmt));
777 I->dropPoisonGeneratingFlags();
785 case Instruction::LShr: {
791 if (
I->hasOneUse()) {
793 if (Inst && Inst->getOpcode() == BinaryOperator::Or) {
795 auto [IID, FShiftArgs] = *Opt;
796 if ((IID == Intrinsic::fshl || IID == Intrinsic::fshr) &&
797 FShiftArgs[0] == FShiftArgs[1]) {
813 if (SignBits >= NumHiDemandedBits)
814 return I->getOperand(0);
823 Constant *RightShiftAmtC = ConstantInt::get(VTy, ShiftAmt);
827 RightShiftAmtC,
DL) ==
C) {
834 if (
match(
I->getOperand(0),
838 X, ConstantInt::get(
X->getType(), Factor->
lshr(ShiftAmt)));
844 APInt DemandedMaskIn(DemandedMask.
shl(ShiftAmt));
847 I->dropPoisonGeneratingFlags();
862 case Instruction::AShr: {
868 if (SignBits >= NumHiDemandedBits)
869 return I->getOperand(0);
875 if (DemandedMask.
isOne()) {
878 I->getOperand(0),
I->getOperand(1),
I->getName());
887 APInt DemandedMaskIn(DemandedMask.
shl(ShiftAmt));
890 bool ShiftedInBitsDemanded = DemandedMask.
countl_zero() < ShiftAmt;
891 if (ShiftedInBitsDemanded)
895 I->dropPoisonGeneratingFlags();
901 if (Known.
Zero[
BitWidth - 1] || !ShiftedInBitsDemanded) {
911 ShiftAmt != 0,
I->isExact());
917 case Instruction::UDiv: {
923 APInt DemandedMaskIn =
928 I->dropPoisonGeneratingFlags();
939 case Instruction::SRem: {
942 if (DemandedMask.
ult(*Rem))
943 return I->getOperand(0);
945 APInt LowBits = *Rem - 1;
956 case Instruction::Call: {
957 bool KnownBitsComputed =
false;
959 switch (
II->getIntrinsicID()) {
960 case Intrinsic::abs: {
961 if (DemandedMask == 1)
962 return II->getArgOperand(0);
965 case Intrinsic::ctpop: {
973 II->getModule(), Intrinsic::ctpop, VTy);
978 case Intrinsic::bswap: {
995 NewVal = BinaryOperator::CreateLShr(
996 II->getArgOperand(0), ConstantInt::get(VTy, NLZ - NTZ));
998 NewVal = BinaryOperator::CreateShl(
999 II->getArgOperand(0), ConstantInt::get(VTy, NTZ - NLZ));
1005 case Intrinsic::ptrmask: {
1006 unsigned MaskWidth =
I->getOperand(1)->getType()->getScalarSizeInBits();
1011 I, 1, (DemandedMask & ~LHSKnown.Zero).zextOrTrunc(MaskWidth),
1012 RHSKnown, Q,
Depth + 1))
1018 Known = LHSKnown & RHSKnown;
1019 KnownBitsComputed =
true;
1034 if (DemandedMask.
isSubsetOf(RHSKnown.One | LHSKnown.Zero))
1035 return I->getOperand(0);
1039 I, 1, (DemandedMask & ~LHSKnown.Zero).zextOrTrunc(MaskWidth)))
1054 if (!LHSKnown.isZero()) {
1055 const unsigned trailingZeros = LHSKnown.countMinTrailingZeros();
1058 uint64_t HighBitsGEPIndex = GEPIndex & ~PointerAlignBits;
1060 GEPIndex & PointerAlignBits & PtrMaskImmediate;
1062 uint64_t MaskedGEPIndex = HighBitsGEPIndex | MaskedLowBitsGEPIndex;
1064 if (MaskedGEPIndex != GEPIndex) {
1067 Type *GEPIndexType =
1068 DL.getIndexType(
GEP->getPointerOperand()->getType());
1070 GEP->getSourceElementType(), InnerPtr,
1071 ConstantInt::get(GEPIndexType, MaskedGEPIndex),
1072 GEP->getName(),
GEP->isInBounds());
1083 case Intrinsic::fshr:
1084 case Intrinsic::fshl: {
1092 if (
II->getIntrinsicID() == Intrinsic::fshr)
1095 APInt DemandedMaskLHS(DemandedMask.
lshr(ShiftAmt));
1097 if (
I->getOperand(0) !=
I->getOperand(1)) {
1103 I->dropPoisonGeneratingReturnAttributes();
1110 if (DemandedMaskLHS.
isSubsetOf(LHSKnown.Zero | LHSKnown.One) &&
1124 LHSKnown <<= ShiftAmt;
1127 KnownBitsComputed =
true;
1130 case Intrinsic::umax: {
1137 CTZ >=
C->getActiveBits())
1138 return II->getArgOperand(0);
1141 case Intrinsic::umin: {
1149 CTZ >=
C->getBitWidth() -
C->countl_one())
1150 return II->getArgOperand(0);
1156 *
II, DemandedMask, Known, KnownBitsComputed);
1164 if (!KnownBitsComputed)
1170 if (
I->getType()->isPointerTy()) {
1171 Align Alignment =
I->getPointerAlignment(
DL);
1179 if (!
I->getType()->isPointerTy() &&
1185 if (Known != ReferenceKnown) {
1186 errs() <<
"Mismatched known bits for " << *
I <<
" in "
1187 <<
I->getFunction()->getName() <<
"\n";
1188 errs() <<
"computeKnownBits(): " << ReferenceKnown <<
"\n";
1189 errs() <<
"SimplifyDemandedBits(): " << Known <<
"\n";
1204 Type *ITy =
I->getType();
1213 switch (
I->getOpcode()) {
1214 case Instruction::And: {
1229 return I->getOperand(0);
1231 return I->getOperand(1);
1235 case Instruction::Or: {
1252 return I->getOperand(0);
1254 return I->getOperand(1);
1258 case Instruction::Xor: {
1274 return I->getOperand(0);
1276 return I->getOperand(1);
1280 case Instruction::Add: {
1288 return I->getOperand(0);
1292 return I->getOperand(1);
1300 case Instruction::Sub: {
1308 return I->getOperand(0);
1317 case Instruction::AShr: {
1330 const APInt *ShiftRC;
1331 const APInt *ShiftLC;
1379 if (!ShlOp1 || !ShrOp1)
1384 unsigned BitWidth = Ty->getScalarSizeInBits();
1393 Known.
Zero &= DemandedMask;
1398 bool isLshr = (Shr->
getOpcode() == Instruction::LShr);
1399 BitMask1 = isLshr ? (BitMask1.
lshr(ShrAmt) << ShlAmt) :
1400 (BitMask1.
ashr(ShrAmt) << ShlAmt);
1402 if (ShrAmt <= ShlAmt) {
1403 BitMask2 <<= (ShlAmt - ShrAmt);
1405 BitMask2 = isLshr ? BitMask2.
lshr(ShrAmt - ShlAmt):
1406 BitMask2.
ashr(ShrAmt - ShlAmt);
1410 if ((BitMask1 & DemandedMask) == (BitMask2 & DemandedMask)) {
1411 if (ShrAmt == ShlAmt)
1418 if (ShrAmt < ShlAmt) {
1420 New = BinaryOperator::CreateShl(VarX, Amt);
1426 New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
1427 BinaryOperator::CreateAShr(VarX, Amt);
1429 New->setIsExact(
true);
1455 bool AllowMultipleUsers) {
1463 assert((DemandedElts & ~EltMask) == 0 &&
"Invalid DemandedElts!");
1467 PoisonElts = EltMask;
1471 if (DemandedElts.
isZero()) {
1472 PoisonElts = EltMask;
1487 for (
unsigned i = 0; i != VWidth; ++i) {
1488 if (!DemandedElts[i]) {
1494 Constant *Elt =
C->getAggregateElement(i);
1495 if (!Elt)
return nullptr;
1504 return NewCV !=
C ? NewCV :
nullptr;
1511 if (!AllowMultipleUsers) {
1515 if (!V->hasOneUse()) {
1524 DemandedElts = EltMask;
1529 if (!
I)
return nullptr;
1531 bool MadeChange =
false;
1532 auto simplifyAndSetOp = [&](
Instruction *Inst,
unsigned OpNum,
1542 APInt PoisonElts2(VWidth, 0);
1543 APInt PoisonElts3(VWidth, 0);
1544 switch (
I->getOpcode()) {
1547 case Instruction::GetElementPtr: {
1565 for (
unsigned i = 0; i <
I->getNumOperands(); i++) {
1569 PoisonElts = EltMask;
1572 if (
I->getOperand(i)->getType()->isVectorTy()) {
1573 APInt PoisonEltsOp(VWidth, 0);
1574 simplifyAndSetOp(
I, i, DemandedElts, PoisonEltsOp);
1579 PoisonElts |= PoisonEltsOp;
1585 case Instruction::InsertElement: {
1592 simplifyAndSetOp(
I, 0, DemandedElts, PoisonElts2);
1599 APInt PreInsertDemandedElts = DemandedElts;
1601 PreInsertDemandedElts.
clearBit(IdxNo);
1609 if (PreInsertDemandedElts == 0 &&
1616 simplifyAndSetOp(
I, 0, PreInsertDemandedElts, PoisonElts);
1620 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
1622 return I->getOperand(0);
1629 case Instruction::ShuffleVector: {
1631 assert(Shuffle->getOperand(0)->getType() ==
1632 Shuffle->getOperand(1)->getType() &&
1633 "Expected shuffle operands to have same type");
1638 if (
all_of(Shuffle->getShuffleMask(), [](
int Elt) { return Elt == 0; }) &&
1644 APInt LeftDemanded(OpWidth, 1);
1645 APInt LHSPoisonElts(OpWidth, 0);
1646 simplifyAndSetOp(
I, 0, LeftDemanded, LHSPoisonElts);
1647 if (LHSPoisonElts[0])
1648 PoisonElts = EltMask;
1654 APInt LeftDemanded(OpWidth, 0), RightDemanded(OpWidth, 0);
1655 for (
unsigned i = 0; i < VWidth; i++) {
1656 if (DemandedElts[i]) {
1657 unsigned MaskVal = Shuffle->getMaskValue(i);
1658 if (MaskVal != -1u) {
1659 assert(MaskVal < OpWidth * 2 &&
1660 "shufflevector mask index out of range!");
1661 if (MaskVal < OpWidth)
1662 LeftDemanded.setBit(MaskVal);
1664 RightDemanded.
setBit(MaskVal - OpWidth);
1669 APInt LHSPoisonElts(OpWidth, 0);
1670 simplifyAndSetOp(
I, 0, LeftDemanded, LHSPoisonElts);
1672 APInt RHSPoisonElts(OpWidth, 0);
1673 simplifyAndSetOp(
I, 1, RightDemanded, RHSPoisonElts);
1686 if (VWidth == OpWidth) {
1687 bool IsIdentityShuffle =
true;
1688 for (
unsigned i = 0; i < VWidth; i++) {
1689 unsigned MaskVal = Shuffle->getMaskValue(i);
1690 if (DemandedElts[i] && i != MaskVal) {
1691 IsIdentityShuffle =
false;
1695 if (IsIdentityShuffle)
1696 return Shuffle->getOperand(0);
1699 bool NewPoisonElts =
false;
1700 unsigned LHSIdx = -1u, LHSValIdx = -1u;
1701 unsigned RHSIdx = -1u, RHSValIdx = -1u;
1702 bool LHSUniform =
true;
1703 bool RHSUniform =
true;
1704 for (
unsigned i = 0; i < VWidth; i++) {
1705 unsigned MaskVal = Shuffle->getMaskValue(i);
1706 if (MaskVal == -1u) {
1708 }
else if (!DemandedElts[i]) {
1709 NewPoisonElts =
true;
1711 }
else if (MaskVal < OpWidth) {
1712 if (LHSPoisonElts[MaskVal]) {
1713 NewPoisonElts =
true;
1716 LHSIdx = LHSIdx == -1u ? i : OpWidth;
1717 LHSValIdx = LHSValIdx == -1u ? MaskVal : OpWidth;
1718 LHSUniform = LHSUniform && (MaskVal == i);
1721 if (RHSPoisonElts[MaskVal - OpWidth]) {
1722 NewPoisonElts =
true;
1725 RHSIdx = RHSIdx == -1u ? i : OpWidth;
1726 RHSValIdx = RHSValIdx == -1u ? MaskVal - OpWidth : OpWidth;
1727 RHSUniform = RHSUniform && (MaskVal - OpWidth == i);
1743 if (LHSIdx < OpWidth && RHSUniform) {
1745 Op = Shuffle->getOperand(1);
1746 Value = CV->getOperand(LHSValIdx);
1750 if (RHSIdx < OpWidth && LHSUniform) {
1752 Op = Shuffle->getOperand(0);
1753 Value = CV->getOperand(RHSValIdx);
1766 if (NewPoisonElts) {
1769 for (
unsigned i = 0; i < VWidth; ++i) {
1773 Elts.
push_back(Shuffle->getMaskValue(i));
1775 Shuffle->setShuffleMask(Elts);
1780 case Instruction::Select: {
1790 simplifyAndSetOp(
I, 0, DemandedElts, PoisonElts);
1794 APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts);
1796 for (
unsigned i = 0; i < VWidth; i++) {
1801 DemandedLHS.clearBit(i);
1807 simplifyAndSetOp(
I, 1, DemandedLHS, PoisonElts2);
1808 simplifyAndSetOp(
I, 2, DemandedRHS, PoisonElts3);
1812 PoisonElts = PoisonElts2 & PoisonElts3;
1815 case Instruction::BitCast: {
1820 APInt InputDemandedElts(InVWidth, 0);
1821 PoisonElts2 =
APInt(InVWidth, 0);
1824 if (VWidth == InVWidth) {
1828 InputDemandedElts = DemandedElts;
1829 }
else if ((VWidth % InVWidth) == 0) {
1833 Ratio = VWidth / InVWidth;
1834 for (
unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1835 if (DemandedElts[OutIdx])
1836 InputDemandedElts.
setBit(OutIdx / Ratio);
1837 }
else if ((InVWidth % VWidth) == 0) {
1841 Ratio = InVWidth / VWidth;
1842 for (
unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1843 if (DemandedElts[InIdx / Ratio])
1844 InputDemandedElts.
setBit(InIdx);
1850 simplifyAndSetOp(
I, 0, InputDemandedElts, PoisonElts2);
1852 if (VWidth == InVWidth) {
1853 PoisonElts = PoisonElts2;
1854 }
else if ((VWidth % InVWidth) == 0) {
1858 for (
unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1859 if (PoisonElts2[OutIdx / Ratio])
1860 PoisonElts.
setBit(OutIdx);
1861 }
else if ((InVWidth % VWidth) == 0) {
1865 for (
unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1868 PoisonElts.
setBit(OutIdx);
1875 case Instruction::FPTrunc:
1876 case Instruction::FPExt:
1877 simplifyAndSetOp(
I, 0, DemandedElts, PoisonElts);
1880 case Instruction::Call: {
1883 switch (
II->getIntrinsicID()) {
1884 case Intrinsic::masked_gather:
1885 case Intrinsic::masked_load: {
1890 DemandedPassThrough(DemandedElts);
1892 for (
unsigned i = 0; i < VWidth; i++) {
1894 if (CElt->isNullValue())
1895 DemandedPtrs.clearBit(i);
1896 else if (CElt->isAllOnesValue())
1902 if (
II->getIntrinsicID() == Intrinsic::masked_gather)
1903 simplifyAndSetOp(
II, 0, DemandedPtrs, PoisonElts2);
1904 simplifyAndSetOp(
II, 3, DemandedPassThrough, PoisonElts3);
1908 PoisonElts = PoisonElts2 & PoisonElts3;
1914 *
II, DemandedElts, PoisonElts, PoisonElts2, PoisonElts3,
1948 if (DemandedElts == 1 && !
X->hasOneUse() && !
Y->hasOneUse() &&
1951 auto findShufBO = [&](
bool MatchShufAsOp0) ->
User * {
1956 Value *OtherOp = MatchShufAsOp0 ?
Y :
X;
1961 Value *ShufOp = MatchShufAsOp0 ?
X :
Y;
1972 if (
DT.dominates(U,
I))
1978 if (
User *ShufBO = findShufBO(
true))
1980 if (
User *ShufBO = findShufBO(
false))
1984 simplifyAndSetOp(
I, 0, DemandedElts, PoisonElts);
1985 simplifyAndSetOp(
I, 1, DemandedElts, PoisonElts2);
1989 PoisonElts &= PoisonElts2;
1997 return MadeChange ?
I :
nullptr;
2010 if (Ty->isAggregateType())
2031 Type *VTy = V->getType();
2035 if (DemandedMask ==
fcNone)
2045 Value *FoldedToConst =
2047 return FoldedToConst == V ? nullptr : FoldedToConst;
2050 if (!
I->hasOneUse())
2054 if (FPOp->hasNoNaNs())
2056 if (FPOp->hasNoInfs())
2059 switch (
I->getOpcode()) {
2060 case Instruction::FNeg: {
2067 case Instruction::Call: {
2070 case Intrinsic::fabs:
2076 case Intrinsic::arithmetic_fence:
2080 case Intrinsic::copysign: {
2086 if ((DemandedMask &
fcNegative) == DemandedMask) {
2088 I->setOperand(1, ConstantFP::get(VTy, -1.0));
2092 if ((DemandedMask &
fcPositive) == DemandedMask) {
2110 case Instruction::Select: {
2117 return I->getOperand(2);
2119 return I->getOperand(1);
2122 Known = KnownLHS | KnownRHS;
2137 Use &U =
I->getOperandUse(OpNo);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
AMDGPU Register Bank Select
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file provides internal interfaces used to implement the InstCombine.
static cl::opt< unsigned > SimplifyDemandedVectorEltsDepthLimit("instcombine-simplify-vector-elts-depth", cl::desc("Depth limit when simplifying vector instructions and their operands"), cl::Hidden, cl::init(10))
static Constant * getFPClassConstant(Type *Ty, FPClassTest Mask)
For floating-point classes that resolve to a single bit pattern, return that value.
static cl::opt< bool > VerifyKnownBits("instcombine-verify-known-bits", cl::desc("Verify that computeKnownBits() and " "SimplifyDemandedBits() are consistent"), cl::Hidden, cl::init(false))
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type.
static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
static Value * simplifyShiftSelectingPackedElement(Instruction *I, const APInt &DemandedMask, InstCombinerImpl &IC, unsigned Depth)
Let N = 2 * M.
This file provides the interface for the instcombine pass implementation.
uint64_t IntrinsicInst * II
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type.
Class for arbitrary precision integers.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
uint64_t getZExtValue() const
Get zero extended value.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
unsigned popcount() const
Count the number of bits set.
LLVM_ABI APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
LLVM_ABI APInt trunc(unsigned width) const
Truncate to new width.
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
LLVM_ABI APInt urem(const APInt &RHS) const
Unsigned remainder operation.
void setSignBit()
Set the sign bit to 1.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool ult(const APInt &RHS) const
Unsigned less than comparison.
void clearAllBits()
Set every bit to 0.
unsigned countr_zero() const
Count the number of trailing zero bits.
unsigned countl_zero() const
The APInt version of std::countl_zero.
void clearLowBits(unsigned loBits)
Set bottom loBits bits to 0.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
APInt shl(unsigned shiftAmt) const
Left-shift function.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
bool isOne() const
Determine if this is a value of 1.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BinaryOps getOpcode() const
LLVM_ABI Intrinsic::ID getIntrinsicID() const
Returns the intrinsic ID of the intrinsic called or Intrinsic::not_intrinsic if the called function i...
This class represents a function call, abstracting a target machine's calling convention.
static CallInst * Create(FunctionType *Ty, Value *F, const Twine &NameStr="", InsertPosition InsertBefore=nullptr)
This is the base class for all instructions that perform data casts.
static LLVM_ABI Constant * getInfinity(Type *Ty, bool Negative=false)
static LLVM_ABI Constant * getZero(Type *Ty, bool Negative=false)
This is the shared class of boolean and integer constants.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
const APInt & getValue() const
Return the constant as an APInt value reference.
static LLVM_ABI Constant * get(ArrayRef< Constant * > V)
This is an important base class in LLVM.
static LLVM_ABI Constant * getIntegerValue(Type *Ty, const APInt &V)
Return the value for an integer or pointer constant, or a vector thereof, with the given scalar value...
static LLVM_ABI Constant * getAllOnesValue(Type *Ty)
LLVM_ABI bool isOneValue() const
Returns true if the value is one.
static LLVM_ABI Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
LLVM_ABI Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
LLVM_ABI bool isNullValue() const
Return true if this is the value that would be returned by getNullValue.
A parsed version of the target data layout string in and methods for querying it.
an instruction for type-safe pointer arithmetic to access elements of arrays and structs
LLVM_ABI Value * CreateSelect(Value *C, Value *True, Value *False, const Twine &Name="", Instruction *MDFrom=nullptr)
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
static InsertElementInst * Create(Value *Vec, Value *NewElt, Value *Idx, const Twine &NameStr="", InsertPosition InsertBefore=nullptr)
KnownFPClass computeKnownFPClass(Value *Val, FastMathFlags FMF, FPClassTest Interested=fcAllFlags, const Instruction *CtxI=nullptr, unsigned Depth=0) const
Value * SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, APInt &PoisonElts, unsigned Depth=0, bool AllowMultipleUsers=false) override
The specified value produces a vector with any number of elements.
bool SimplifyDemandedBits(Instruction *I, unsigned Op, const APInt &DemandedMask, KnownBits &Known, const SimplifyQuery &Q, unsigned Depth=0) override
This form of SimplifyDemandedBits simplifies the specified instruction operand if possible,...
std::optional< std::pair< Intrinsic::ID, SmallVector< Value *, 3 > > > convertOrOfShiftsToFunnelShift(Instruction &Or)
Value * simplifyShrShlDemandedBits(Instruction *Shr, const APInt &ShrOp1, Instruction *Shl, const APInt &ShlOp1, const APInt &DemandedMask, KnownBits &Known)
Helper routine of SimplifyDemandedUseBits.
Value * SimplifyDemandedUseBits(Instruction *I, const APInt &DemandedMask, KnownBits &Known, const SimplifyQuery &Q, unsigned Depth=0)
Attempts to replace I with a simpler value based on the demanded bits.
bool SimplifyDemandedFPClass(Instruction *I, unsigned Op, FPClassTest DemandedMask, KnownFPClass &Known, unsigned Depth=0)
bool SimplifyDemandedInstructionBits(Instruction &Inst)
Tries to simplify operands to an integer instruction based on its demanded bits.
Value * SimplifyMultipleUseDemandedBits(Instruction *I, const APInt &DemandedMask, KnownBits &Known, const SimplifyQuery &Q, unsigned Depth=0)
Helper routine of SimplifyDemandedUseBits.
Value * SimplifyDemandedUseFPClass(Value *V, FPClassTest DemandedMask, KnownFPClass &Known, Instruction *CxtI, unsigned Depth=0)
Attempts to replace V with a simpler value based on the demanded floating-point classes.
unsigned ComputeNumSignBits(const Value *Op, const Instruction *CxtI=nullptr, unsigned Depth=0) const
Instruction * replaceInstUsesWith(Instruction &I, Value *V)
A combiner-aware RAUW-like routine.
void replaceUse(Use &U, Value *NewValue)
Replace use and add the previously used value to the worklist.
InstructionWorklist & Worklist
A worklist of the instructions that need to be simplified.
Instruction * InsertNewInstWith(Instruction *New, BasicBlock::iterator Old)
Same as InsertNewInstBefore, but also sets the debug loc.
void computeKnownBits(const Value *V, KnownBits &Known, const Instruction *CxtI, unsigned Depth=0) const
std::optional< Value * > targetSimplifyDemandedVectorEltsIntrinsic(IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp)
Instruction * replaceOperand(Instruction &I, unsigned OpNum, Value *V)
Replace operand of instruction and add old operand to the worklist.
std::optional< Value * > targetSimplifyDemandedUseBitsIntrinsic(IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed)
LLVM_ABI bool hasNoUnsignedWrap() const LLVM_READONLY
Determine whether the no unsigned wrap flag is set.
LLVM_ABI bool hasNoSignedWrap() const LLVM_READONLY
Determine whether the no signed wrap flag is set.
LLVM_ABI bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
LLVM_ABI void setIsExact(bool b=true)
Set or clear the exact flag on this instruction, which must be an operator which supports this flag.
A wrapper class for inspecting calls to intrinsic functions.
bool hasNoSignedWrap() const
Test whether this operation is known to never undergo signed overflow, aka the nsw property.
bool hasNoUnsignedWrap() const
Test whether this operation is known to never undergo unsigned overflow, aka the nuw property.
static LLVM_ABI PoisonValue * get(Type *T)
Static factory methods - Return an 'poison' object of the specified type.
This class represents the LLVM 'select' instruction.
const Value * getCondition() const
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
The instances of the Type class are immutable: once they are created, they are never changed.
static LLVM_ABI IntegerType * getInt64Ty(LLVMContext &C)
bool isVectorTy() const
True if this is an instance of VectorType.
bool isIntOrIntVectorTy() const
Return true if this is an integer type or a vector of integer types.
LLVM_ABI unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
static LLVM_ABI UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
A Use represents the edge between a Value definition and its users.
Value * getOperand(unsigned i) const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
bool hasOneUse() const
Return true if there is exactly one use of this value.
iterator_range< user_iterator > users()
bool hasUseList() const
Check if this Value has a use-list.
LLVM_ABI StringRef getName() const
Return a constant reference to the value's name.
LLVM_ABI void takeName(Value *V)
Transfer the name from V to this value.
Base class of all SIMD vector types.
This class represents zero extension of integer types.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
LLVM_ABI Function * getOrInsertDeclaration(Module *M, ID id, ArrayRef< Type * > Tys={})
Look up the Function declaration of the intrinsic id in the Module M.
BinaryOp_match< SrcTy, SpecificConstantMatch, TargetOpcode::G_XOR, true > m_Not(const SrcTy &&Src)
Matches a register not-ed by a G_XOR.
OneUse_match< SubPat > m_OneUse(const SubPat &SP)
class_match< PoisonValue > m_Poison()
Match an arbitrary poison constant.
cst_pred_ty< is_lowbit_mask > m_LowBitMask()
Match an integer or vector with only the low bit(s) set.
PtrAdd_match< PointerOpTy, OffsetOpTy > m_PtrAdd(const PointerOpTy &PointerOp, const OffsetOpTy &OffsetOp)
Matches GEP with i8 source element type.
BinaryOp_match< LHS, RHS, Instruction::Add > m_Add(const LHS &L, const RHS &R)
class_match< BinaryOperator > m_BinOp()
Match an arbitrary binary operation and ignore it.
BinaryOp_match< LHS, RHS, Instruction::AShr > m_AShr(const LHS &L, const RHS &R)
ap_match< APInt > m_APInt(const APInt *&Res)
Match a ConstantInt or splatted ConstantVector, binding the specified pointer to the contained APInt.
specific_intval< false > m_SpecificInt(const APInt &V)
Match a specific integer value or vector with all elements equal to the value.
bool match(Val *V, const Pattern &P)
specificval_ty m_Specific(const Value *V)
Match if we have a specific specified value.
BinOpPred_match< LHS, RHS, is_right_shift_op > m_Shr(const LHS &L, const RHS &R)
Matches logical shift operations.
TwoOps_match< Val_t, Idx_t, Instruction::ExtractElement > m_ExtractElt(const Val_t &Val, const Idx_t &Idx)
Matches ExtractElementInst.
class_match< ConstantInt > m_ConstantInt()
Match an arbitrary ConstantInt and ignore it.
IntrinsicID_match m_Intrinsic()
Match intrinsic calls like this: m_Intrinsic<Intrinsic::fabs>(m_Value(X))
BinaryOp_match< LHS, RHS, Instruction::Mul > m_Mul(const LHS &L, const RHS &R)
TwoOps_match< V1_t, V2_t, Instruction::ShuffleVector > m_Shuffle(const V1_t &v1, const V2_t &v2)
Matches ShuffleVectorInst independently of mask value.
CastInst_match< OpTy, ZExtInst > m_ZExt(const OpTy &Op)
Matches ZExt.
match_immconstant_ty m_ImmConstant()
Match an arbitrary immediate Constant and ignore it.
DisjointOr_match< LHS, RHS, true > m_c_DisjointOr(const LHS &L, const RHS &R)
BinaryOp_match< LHS, RHS, Instruction::Add, true > m_c_Add(const LHS &L, const RHS &R)
Matches a Add with LHS and RHS in either order.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
AnyBinaryOp_match< LHS, RHS, true > m_c_BinOp(const LHS &L, const RHS &R)
Matches a BinaryOperator with LHS and RHS in either order.
BinaryOp_match< LHS, RHS, Instruction::LShr > m_LShr(const LHS &L, const RHS &R)
CmpClass_match< LHS, RHS, ICmpInst > m_ICmp(CmpPredicate &Pred, const LHS &L, const RHS &R)
BinaryOp_match< LHS, RHS, Instruction::Shl > m_Shl(const LHS &L, const RHS &R)
auto m_Undef()
Match an arbitrary undef constant.
CastInst_match< OpTy, SExtInst > m_SExt(const OpTy &Op)
Matches SExt.
is_zero m_Zero()
Match any null constant or a vector with all elements equal to 0.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI bool haveNoCommonBitsSet(const WithCache< const Value * > &LHSCache, const WithCache< const Value * > &RHSCache, const SimplifyQuery &SQ)
Return true if LHS and RHS have no common bits set.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
LLVM_ABI void computeKnownBitsFromContext(const Value *V, KnownBits &Known, const SimplifyQuery &Q, unsigned Depth=0)
Merge bits known from context-dependent facts into Known.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
constexpr T alignDown(U Value, V Align, W Skew=0)
Returns the largest unsigned integer less than or equal to Value and is Skew mod Align.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
gep_type_iterator gep_type_end(const User *GEP)
constexpr unsigned MaxAnalysisRecursionDepth
LLVM_ABI void adjustKnownBitsForSelectArm(KnownBits &Known, Value *Cond, Value *Arm, bool Invert, const SimplifyQuery &Q, unsigned Depth=0)
Adjust Known for the given select Arm to include information from the select Cond.
LLVM_ABI FPClassTest fneg(FPClassTest Mask)
Return the test mask which returns true if the value's sign bit is flipped.
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
LLVM_ABI void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true, unsigned Depth=0)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
LLVM_ABI FPClassTest inverse_fabs(FPClassTest Mask)
Return the test mask which returns true after fabs is applied to the value.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
LLVM_ABI Constant * ConstantFoldBinaryOpOperands(unsigned Opcode, Constant *LHS, Constant *RHS, const DataLayout &DL)
Attempt to constant fold a binary operation with the specified operands.
constexpr int PoisonMaskElem
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ Mul
Product of integers.
@ Xor
Bitwise or logical XOR of integers.
LLVM_ABI FPClassTest unknown_sign(FPClassTest Mask)
Return the test mask which returns true if the value could have the same set of classes,...
DWARFExpression::Operation Op
constexpr unsigned BitWidth
LLVM_ABI KnownBits analyzeKnownBitsFromAndXorOr(const Operator *I, const KnownBits &KnownLHS, const KnownBits &KnownRHS, const SimplifyQuery &SQ, unsigned Depth=0)
Using KnownBits LHS/RHS produce the known bits for logic op (and/xor/or).
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
gep_type_iterator gep_type_begin(const User *GEP)
unsigned Log2(Align A)
Returns the log2 of the alignment.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
KnownBits anyextOrTrunc(unsigned BitWidth) const
Return known bits for an "any" extension or truncation of the value we're tracking.
bool isNonNegative() const
Returns true if this value is known to be non-negative.
void makeNonNegative()
Make this value non-negative.
static LLVM_ABI KnownBits ashr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for ashr(LHS, RHS).
unsigned getBitWidth() const
Get the bit width of this value.
void resetAll()
Resets the known state of all bits.
KnownBits unionWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for either this or RHS or both.
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
static KnownBits add(const KnownBits &LHS, const KnownBits &RHS, bool NSW=false, bool NUW=false)
Compute knownbits resulting from addition of LHS and RHS.
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
APInt getMaxValue() const
Return the maximal unsigned value possible given these KnownBits.
static LLVM_ABI KnownBits srem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for srem(LHS, RHS).
static LLVM_ABI KnownBits udiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for udiv(LHS, RHS).
bool isNegative() const
Returns true if this value is known to be negative.
static KnownBits sub(const KnownBits &LHS, const KnownBits &RHS, bool NSW=false, bool NUW=false)
Compute knownbits resulting from subtraction of LHS and RHS.
static LLVM_ABI KnownBits shl(const KnownBits &LHS, const KnownBits &RHS, bool NUW=false, bool NSW=false, bool ShAmtNonZero=false)
Compute known bits for shl(LHS, RHS).
FPClassTest KnownFPClasses
Floating-point classes the value could be one of.
void copysign(const KnownFPClass &Sign)
bool isKnownNever(FPClassTest Mask) const
Return true if it's known this can never be one of the mask entries.