LLVM 20.0.0git
ARMRegisterBankInfo.h
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1//===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the RegisterBankInfo class for ARM.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
14#define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
15
17
18#define GET_REGBANK_DECLARATIONS
19#include "ARMGenRegisterBank.inc"
20
21namespace llvm {
22
23class TargetRegisterInfo;
24
26#define GET_TARGET_REGBANK_CLASS
27#include "ARMGenRegisterBank.inc"
28};
29
30/// This class provides the information for the target register banks.
32public:
34
35 const InstructionMapping &
36 getInstrMapping(const MachineInstr &MI) const override;
37};
38} // End llvm namespace.
39#endif
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
This class provides the information for the target register banks.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Holds all the information related to register banks.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18