LLVM 20.0.0git
AVRAsmBackend.cpp
Go to the documentation of this file.
1//===-- AVRAsmBackend.cpp - AVR Asm Backend ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the AVRAsmBackend class.
10//
11//===----------------------------------------------------------------------===//
12
18#include "llvm/MC/MCAssembler.h"
19#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCValue.h"
29
30namespace adjust {
31
32using namespace llvm;
33
34static void signed_width(unsigned Width, uint64_t Value,
35 std::string Description, const MCFixup &Fixup,
36 MCContext *Ctx) {
37 if (!isIntN(Width, Value)) {
38 std::string Diagnostic = "out of range " + Description;
39
40 int64_t Min = minIntN(Width);
41 int64_t Max = maxIntN(Width);
42
43 Diagnostic += " (expected an integer in the range " + std::to_string(Min) +
44 " to " + std::to_string(Max) + ")";
45
46 Ctx->reportError(Fixup.getLoc(), Diagnostic);
47 }
48}
49
50static void unsigned_width(unsigned Width, uint64_t Value,
51 std::string Description, const MCFixup &Fixup,
52 MCContext *Ctx) {
53 if (!isUIntN(Width, Value)) {
54 std::string Diagnostic = "out of range " + Description;
55
56 int64_t Max = maxUIntN(Width);
57
58 Diagnostic +=
59 " (expected an integer in the range 0 to " + std::to_string(Max) + ")";
60
61 Ctx->reportError(Fixup.getLoc(), Diagnostic);
62 }
63}
64
65/// Adjusts the value of a branch target before fixup application.
66static void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
67 MCContext *Ctx) {
68 // We have one extra bit of precision because the value is rightshifted by
69 // one.
70 unsigned_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
71
72 // Rightshifts the value by one.
74}
75
76/// Adjusts the value of a relative branch target before fixup application.
77static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup,
78 uint64_t &Value, MCContext *Ctx) {
79 // Jumps are relative to the current instruction.
80 Value -= 2;
81
82 // We have one extra bit of precision because the value is rightshifted by
83 // one.
84 Size += 1;
85
86 if (!isIntN(Size, Value) &&
87 Ctx->getSubtargetInfo()->hasFeature(AVR::FeatureWrappingRjmp)) {
88 const int32_t FlashSize = 0x2000;
89 int32_t SignedValue = Value;
90
91 uint64_t WrappedValue = SignedValue > 0 ? (uint64_t)(Value - FlashSize)
92 : (uint64_t)(FlashSize + Value);
93
94 if (isIntN(Size, WrappedValue)) {
95 Value = WrappedValue;
96 }
97 }
98
99 signed_width(Size, Value, std::string("branch target"), Fixup, Ctx);
100
101 // Rightshifts the value by one.
103}
104
105/// 22-bit absolute fixup.
106///
107/// Resolves to:
108/// 1001 kkkk 010k kkkk kkkk kkkk 111k kkkk
109///
110/// Offset of 0 (so the result is left shifted by 3 bits before application).
111static void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
112 MCContext *Ctx) {
114
115 auto top = Value & (0xf00000 << 6); // the top four bits
116 auto middle = Value & (0x1ffff << 5); // the middle 13 bits
117 auto bottom = Value & 0x1f; // end bottom 5 bits
118
119 Value = (top << 6) | (middle << 3) | (bottom << 0);
120}
121
122/// 7-bit PC-relative fixup.
123///
124/// Resolves to:
125/// 0000 00kk kkkk k000
126/// Offset of 0 (so the result is left shifted by 3 bits before application).
127static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
128 MCContext *Ctx) {
130
131 // Because the value may be negative, we must mask out the sign bits
132 Value &= 0x7f;
133}
134
135/// 12-bit PC-relative fixup.
136/// Yes, the fixup is 12 bits even though the name says otherwise.
137///
138/// Resolves to:
139/// 0000 kkkk kkkk kkkk
140/// Offset of 0 (so the result isn't left-shifted before application).
141static void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
142 MCContext *Ctx) {
144
145 // Because the value may be negative, we must mask out the sign bits
146 Value &= 0xfff;
147}
148
149/// 6-bit fixup for the immediate operand of the STD/LDD family of
150/// instructions.
151///
152/// Resolves to:
153/// 10q0 qq10 0000 1qqq
154static void fixup_6(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx) {
155 unsigned_width(6, Value, std::string("immediate"), Fixup, Ctx);
156
157 Value = ((Value & 0x20) << 8) | ((Value & 0x18) << 7) | (Value & 0x07);
158}
159
160/// 6-bit fixup for the immediate operand of the ADIW family of
161/// instructions.
162///
163/// Resolves to:
164/// 0000 0000 kk00 kkkk
166 MCContext *Ctx) {
167 unsigned_width(6, Value, std::string("immediate"), Fixup, Ctx);
168
169 Value = ((Value & 0x30) << 2) | (Value & 0x0f);
170}
171
172/// 5-bit port number fixup on the SBIC family of instructions.
173///
174/// Resolves to:
175/// 0000 0000 AAAA A000
176static void fixup_port5(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx) {
177 unsigned_width(5, Value, std::string("port number"), Fixup, Ctx);
178
179 Value &= 0x1f;
180
181 Value <<= 3;
182}
183
184/// 6-bit port number fixup on the `IN` family of instructions.
185///
186/// Resolves to:
187/// 1011 0AAd dddd AAAA
188static void fixup_port6(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx) {
189 unsigned_width(6, Value, std::string("port number"), Fixup, Ctx);
190
191 Value = ((Value & 0x30) << 5) | (Value & 0x0f);
192}
193
194/// 7-bit data space address fixup for the LDS/STS instructions on AVRTiny.
195///
196/// Resolves to:
197/// 1010 ikkk dddd kkkk
199 MCContext *Ctx) {
200 unsigned_width(7, Value, std::string("immediate"), Fixup, Ctx);
201 Value = ((Value & 0x70) << 8) | (Value & 0x0f);
202}
203
204/// Adjusts a program memory address.
205/// This is a simple right-shift.
206static void pm(uint64_t &Value) { Value >>= 1; }
207
208/// Fixups relating to the LDI instruction.
209namespace ldi {
210
211/// Adjusts a value to fix up the immediate of an `LDI Rd, K` instruction.
212///
213/// Resolves to:
214/// 0000 KKKK 0000 KKKK
215/// Offset of 0 (so the result isn't left-shifted before application).
216static void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
217 MCContext *Ctx) {
218 uint64_t upper = Value & 0xf0;
219 uint64_t lower = Value & 0x0f;
220
221 Value = (upper << 4) | lower;
222}
223
224static void neg(uint64_t &Value) { Value *= -1; }
225
226static void lo8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
227 MCContext *Ctx) {
228 Value &= 0xff;
229 ldi::fixup(Size, Fixup, Value, Ctx);
230}
231
232static void hi8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
233 MCContext *Ctx) {
234 Value = (Value & 0xff00) >> 8;
235 ldi::fixup(Size, Fixup, Value, Ctx);
236}
237
238static void hh8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
239 MCContext *Ctx) {
240 Value = (Value & 0xff0000) >> 16;
241 ldi::fixup(Size, Fixup, Value, Ctx);
242}
243
244static void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
245 MCContext *Ctx) {
246 Value = (Value & 0xff000000) >> 24;
247 ldi::fixup(Size, Fixup, Value, Ctx);
248}
249
250} // namespace ldi
251} // namespace adjust
252
253namespace llvm {
254
255// Prepare value for the target space for it
257 const MCValue &Target, uint64_t &Value,
258 MCContext *Ctx) const {
259 // The size of the fixup in bits.
261
262 unsigned Kind = Fixup.getKind();
263 switch (Kind) {
264 default:
265 llvm_unreachable("unhandled fixup");
268 break;
271 break;
272 case AVR::fixup_call:
274 break;
275 case AVR::fixup_ldi:
277 break;
280 break;
285 break;
288 break;
293 break;
296 if (Kind == AVR::fixup_hh8_ldi_pm)
298
300 break;
303 break;
304
307 if (Kind == AVR::fixup_lo8_ldi_pm_neg)
309
312 break;
315 if (Kind == AVR::fixup_hi8_ldi_pm_neg)
317
320 break;
323 if (Kind == AVR::fixup_hh8_ldi_pm_neg)
325
328 break;
332 break;
333 case AVR::fixup_16:
334 adjust::unsigned_width(16, Value, std::string("port number"), Fixup, Ctx);
335
336 Value &= 0xffff;
337 break;
338 case AVR::fixup_16_pm:
339 Value >>= 1; // Flash addresses are always shifted.
340 adjust::unsigned_width(16, Value, std::string("port number"), Fixup, Ctx);
341
342 Value &= 0xffff;
343 break;
344
345 case AVR::fixup_6:
347 break;
350 break;
351
352 case AVR::fixup_port5:
354 break;
355
356 case AVR::fixup_port6:
358 break;
359
362 break;
363
364 // Fixups which do not require adjustments.
365 case FK_Data_1:
366 case FK_Data_2:
367 case FK_Data_4:
368 case FK_Data_8:
369 break;
370
371 case FK_GPRel_4:
372 llvm_unreachable("don't know how to adjust this fixup");
373 break;
374 }
375}
376
377std::unique_ptr<MCObjectTargetWriter>
380}
381
383 const MCValue &Target,
385 bool IsResolved,
386 const MCSubtargetInfo *STI) const {
387 if (Fixup.getKind() >= FirstLiteralRelocationKind)
388 return;
389 adjustFixupValue(Fixup, Target, Value, &Asm.getContext());
390 if (Value == 0)
391 return; // Doesn't change encoding.
392
394
395 // The number of bits in the fixup mask
396 auto NumBits = Info.TargetSize + Info.TargetOffset;
397 auto NumBytes = (NumBits / 8) + ((NumBits % 8) == 0 ? 0 : 1);
398
399 // Shift the value into position.
400 Value <<= Info.TargetOffset;
401
402 unsigned Offset = Fixup.getOffset();
403 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
404
405 // For each byte of the fragment that the fixup touches, mask in the
406 // bits from the fixup value.
407 for (unsigned i = 0; i < NumBytes; ++i) {
408 uint8_t mask = (((Value >> (i * 8)) & 0xff));
409 Data[Offset + i] |= mask;
410 }
411}
412
413std::optional<MCFixupKind> AVRAsmBackend::getFixupKind(StringRef Name) const {
414 unsigned Type;
416#define ELF_RELOC(X, Y) .Case(#X, Y)
417#include "llvm/BinaryFormat/ELFRelocs/AVR.def"
418#undef ELF_RELOC
419 .Case("BFD_RELOC_NONE", ELF::R_AVR_NONE)
420 .Case("BFD_RELOC_16", ELF::R_AVR_16)
421 .Case("BFD_RELOC_32", ELF::R_AVR_32)
422 .Default(-1u);
423 if (Type != -1u)
424 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
425 return std::nullopt;
426}
427
429 // NOTE: Many AVR fixups work on sets of non-contignous bits. We work around
430 // this by saying that the fixup is the size of the entire instruction.
431 const static MCFixupKindInfo Infos[AVR::NumTargetFixupKinds] = {
432 // This table *must* be in same the order of fixup_* kinds in
433 // AVRFixupKinds.h.
434 //
435 // name offset bits flags
436 {"fixup_32", 0, 32, 0},
437
438 {"fixup_7_pcrel", 3, 7, MCFixupKindInfo::FKF_IsPCRel},
439 {"fixup_13_pcrel", 0, 12, MCFixupKindInfo::FKF_IsPCRel},
440
441 {"fixup_16", 0, 16, 0},
442 {"fixup_16_pm", 0, 16, 0},
443
444 {"fixup_ldi", 0, 8, 0},
445
446 {"fixup_lo8_ldi", 0, 8, 0},
447 {"fixup_hi8_ldi", 0, 8, 0},
448 {"fixup_hh8_ldi", 0, 8, 0},
449 {"fixup_ms8_ldi", 0, 8, 0},
450
451 {"fixup_lo8_ldi_neg", 0, 8, 0},
452 {"fixup_hi8_ldi_neg", 0, 8, 0},
453 {"fixup_hh8_ldi_neg", 0, 8, 0},
454 {"fixup_ms8_ldi_neg", 0, 8, 0},
455
456 {"fixup_lo8_ldi_pm", 0, 8, 0},
457 {"fixup_hi8_ldi_pm", 0, 8, 0},
458 {"fixup_hh8_ldi_pm", 0, 8, 0},
459
460 {"fixup_lo8_ldi_pm_neg", 0, 8, 0},
461 {"fixup_hi8_ldi_pm_neg", 0, 8, 0},
462 {"fixup_hh8_ldi_pm_neg", 0, 8, 0},
463
464 {"fixup_call", 0, 22, 0},
465
466 {"fixup_6", 0, 16, 0}, // non-contiguous
467 {"fixup_6_adiw", 0, 6, 0},
468
469 {"fixup_lo8_ldi_gs", 0, 8, 0},
470 {"fixup_hi8_ldi_gs", 0, 8, 0},
471
472 {"fixup_8", 0, 8, 0},
473 {"fixup_8_lo8", 0, 8, 0},
474 {"fixup_8_hi8", 0, 8, 0},
475 {"fixup_8_hlo8", 0, 8, 0},
476
477 {"fixup_diff8", 0, 8, 0},
478 {"fixup_diff16", 0, 16, 0},
479 {"fixup_diff32", 0, 32, 0},
480
481 {"fixup_lds_sts_16", 0, 16, 0},
482
483 {"fixup_port6", 0, 16, 0}, // non-contiguous
484 {"fixup_port5", 3, 5, 0},
485 };
486
487 // Fixup kinds from .reloc directive are like R_AVR_NONE. They do not require
488 // any extra processing.
489 if (Kind >= FirstLiteralRelocationKind)
491
492 if (Kind < FirstTargetFixupKind)
494
495 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
496 "Invalid kind!");
497
498 return Infos[Kind - FirstTargetFixupKind];
499}
500
502 const MCSubtargetInfo *STI) const {
503 // If the count is not 2-byte aligned, we must be writing data into the text
504 // section (otherwise we have unaligned instructions, and thus have far
505 // bigger problems), so just write zeros instead.
506 assert((Count % 2) == 0 && "NOP instructions must be 2 bytes");
507
508 OS.write_zeros(Count);
509 return true;
510}
511
513 const MCFixup &Fixup,
514 const MCValue &Target,
515 const MCSubtargetInfo *STI) {
516 switch ((unsigned)Fixup.getKind()) {
517 default:
518 return Fixup.getKind() >= FirstLiteralRelocationKind;
521 // Always resolve relocations for PC-relative branches
522 return false;
523 case AVR::fixup_call:
524 return true;
525 }
526}
527
529 const MCRegisterInfo &MRI,
530 const llvm::MCTargetOptions &TO) {
531 return new AVRAsmBackend(STI.getTargetTriple().getOS());
532}
533
534} // end of namespace llvm
unsigned const MachineRegisterInfo * MRI
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
std::string Name
uint64_t Size
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Utilities for manipulating generated AVR machine code.
Definition: AVRAsmBackend.h:29
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
void adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t &Value, MCContext *Ctx=nullptr) const
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Definition: AVRAsmBackend.h:48
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI) override
Hook to check if a relocation is needed for some target specific reason.
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Context object for machine code objects.
Definition: MCContext.h:83
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1072
const MCSubtargetInfo * getSubtargetInfo() const
Definition: MCContext.h:418
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:310
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:392
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
static void hi8(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
static void neg(uint64_t &Value)
static void lo8(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
static void hh8(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
static void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
Adjusts a value to fix up the immediate of an LDI Rd, K instruction.
static void unsigned_width(unsigned Width, uint64_t Value, std::string Description, const MCFixup &Fixup, MCContext *Ctx)
static void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
Adjusts the value of a branch target before fixup application.
static void fixup_lds_sts_16(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
7-bit data space address fixup for the LDS/STS instructions on AVRTiny.
static void fixup_6(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
6-bit fixup for the immediate operand of the STD/LDD family of instructions.
static void fixup_6_adiw(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
6-bit fixup for the immediate operand of the ADIW family of instructions.
static void fixup_port5(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
5-bit port number fixup on the SBIC family of instructions.
static void fixup_port6(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
6-bit port number fixup on the IN family of instructions.
static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
7-bit PC-relative fixup.
static void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
12-bit PC-relative fixup.
static void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
22-bit absolute fixup.
static void signed_width(unsigned Width, uint64_t Value, std::string Description, const MCFixup &Fixup, MCContext *Ctx)
static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx)
Adjusts the value of a relative branch target before fixup application.
static void pm(uint64_t &Value)
Adjusts a program memory address.
void adjustBranchTarget(T &val)
Adjusts the value of a branch target.
@ fixup_16_pm
A 16-bit program memory address.
Definition: AVRFixupKinds.h:46
@ fixup_16
A 16-bit address.
Definition: AVRFixupKinds.h:44
@ fixup_call
A 22-bit fixup for the target of a CALL k or JMP k instruction.
@ fixup_hh8_ldi
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 24-bit value ...
Definition: AVRFixupKinds.h:59
@ fixup_ms8_ldi_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated 32-bi...
Definition: AVRFixupKinds.h:75
@ fixup_lo8_ldi_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the lower 8 bits of a negated 16-bi...
Definition: AVRFixupKinds.h:66
@ fixup_6_adiw
A symbol+addr fixup for the `LDD <x>+<n>, <r>" family of instructions.
@ fixup_ms8_ldi
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 32-bit value ...
Definition: AVRFixupKinds.h:62
@ fixup_7_pcrel
A 7-bit PC-relative fixup for the family of conditional branches which take 7-bit targets (BRNE,...
Definition: AVRFixupKinds.h:32
@ NumTargetFixupKinds
@ fixup_ldi
Replaces the 8-bit immediate with another value.
Definition: AVRFixupKinds.h:49
@ fixup_lo8_ldi
Replaces the immediate operand of a 16-bit Rd, K instruction with the lower 8 bits of a 16-bit value ...
Definition: AVRFixupKinds.h:53
@ fixup_hi8_ldi_pm_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated 16-bi...
Definition: AVRFixupKinds.h:96
@ fixup_hi8_ldi
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 16-bit value ...
Definition: AVRFixupKinds.h:56
@ fixup_lo8_ldi_pm
Replaces the immediate operand of a 16-bit Rd, K instruction with the lower 8 bits of a 16-bit progra...
Definition: AVRFixupKinds.h:79
@ fixup_port6
A 6-bit port address.
@ fixup_hh8_ldi_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated 24-bi...
Definition: AVRFixupKinds.h:72
@ fixup_hh8_ldi_pm
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 24-bit progra...
Definition: AVRFixupKinds.h:87
@ fixup_port5
A 5-bit port address.
@ fixup_lo8_ldi_pm_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the lower 8 bits of a negated 16-bi...
Definition: AVRFixupKinds.h:92
@ fixup_hi8_ldi_pm
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 16-bit progra...
Definition: AVRFixupKinds.h:83
@ fixup_hh8_ldi_pm_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated 24-bi...
@ fixup_13_pcrel
A 12-bit PC-relative fixup for the family of branches which take 12-bit targets (RJMP,...
Definition: AVRFixupKinds.h:41
@ fixup_hi8_ldi_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated 16-bi...
Definition: AVRFixupKinds.h:69
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
int64_t maxIntN(int64_t N)
Gets the maximum value for a N-bit signed integer.
Definition: MathExtras.h:244
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:255
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_GPRel_4
A four-byte gp relative fixup.
Definition: MCFixup.h:34
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
std::unique_ptr< MCObjectTargetWriter > createAVRELFObjectWriter(uint8_t OSABI)
Creates an ELF object writer for AVR.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:260
int64_t minIntN(int64_t N)
Gets the minimum value for a N-bit signed integer.
Definition: MathExtras.h:235
MCAsmBackend * createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const llvm::MCTargetOptions &TO)
Creates an assembly backend for AVR.
uint64_t maxUIntN(uint64_t N)
Gets the maximum value for a N-bit unsigned integer.
Definition: MathExtras.h:219
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
unsigned TargetSize
The number of bits written by this fixup.