28#define DEBUG_TYPE "asm-printer"
31#define PRINT_ALIAS_INSTR
32#include "LanaiGenAsmWriter.inc"
41 OS <<
"\t" << Alias <<
" ";
49 unsigned AluCode =
MI->getOperand(3).getImm();
51 (
MI->getOperand(2).getImm() == AddOffset ||
52 MI->getOperand(2).getImm() == -AddOffset);
56 unsigned AluCode =
MI->getOperand(3).getImm();
61 unsigned AluCode =
MI->getOperand(3).getImm();
66 if (
MI->getOperand(2).getImm() < 0)
71bool LanaiInstPrinter::printMemoryLoadIncrement(
const MCInst *
MI,
82 OS <<
"\t" << Opcode <<
"\t[%"
90bool LanaiInstPrinter::printMemoryStoreIncrement(
const MCInst *
MI,
110 switch (
MI->getOpcode()) {
116 return printMemoryLoadIncrement(
MI,
OS,
"ld", 4);
118 return printMemoryLoadIncrement(
MI,
OS,
"ld.h", 2);
120 return printMemoryLoadIncrement(
MI,
OS,
"uld.h", 2);
122 return printMemoryLoadIncrement(
MI,
OS,
"ld.b", 1);
124 return printMemoryLoadIncrement(
MI,
OS,
"uld.b", 1);
130 return printMemoryStoreIncrement(
MI,
OS,
"st", 4);
132 return printMemoryStoreIncrement(
MI,
OS,
"st.h", 2);
134 return printMemoryStoreIncrement(
MI,
OS,
"st.b", 1);
151 assert((Modifier ==
nullptr || Modifier[0] == 0) &&
"No modifiers supported");
158 assert(
Op.isExpr() &&
"Expected an expression");
170 assert(
Op.isExpr() &&
"Expected an expression");
184 assert(
Op.isExpr() &&
"Expected an expression");
196 assert(
Op.isExpr() &&
"Expected an expression");
208 assert(
Op.isExpr() &&
"Expected an expression");
215 assert(RegOp.
isReg() &&
"Register operand expected");
225template <
unsigned SizeInBits>
230 if (OffsetOp.
isImm()) {
231 assert(isInt<SizeInBits>(OffsetOp.
getImm()) &&
"Constant value truncated");
241 const MCOperand &OffsetOp =
MI->getOperand(OpNo + 1);
243 const unsigned AluCode = AluOp.
getImm();
246 printMemoryImmediateOffset<16>(
MAI, OffsetOp,
OS);
256 const MCOperand &OffsetOp =
MI->getOperand(OpNo + 1);
258 const unsigned AluCode = AluOp.
getImm();
277 const MCOperand &OffsetOp =
MI->getOperand(OpNo + 1);
279 const unsigned AluCode = AluOp.
getImm();
282 printMemoryImmediateOffset<10>(
MAI, OffsetOp,
OS);
296 OS << lanaiCondCodeToString(
CC);
307 OS <<
"." << lanaiCondCodeToString(
CC);
static bool isPostIncrementForm(const MCInst *MI, int AddOffset)
static StringRef decIncOperator(const MCInst *MI)
static void printMemoryBaseRegister(raw_ostream &OS, const unsigned AluCode, const MCOperand &RegOp)
static bool usesGivenOffset(const MCInst *MI, int AddOffset)
static void printMemoryImmediateOffset(const MCAsmInfo &MAI, const MCOperand &OffsetOp, raw_ostream &OS)
static bool isPreIncrementForm(const MCInst *MI, int AddOffset)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
void printMemRrOperand(const MCInst *MI, int OpNo, raw_ostream &O, const char *Modifier=nullptr)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
static const char * getRegisterName(MCRegister Reg)
bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS)
void printMemImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printMemRiOperand(const MCInst *MI, int OpNo, raw_ostream &O, const char *Modifier=nullptr)
void printHi16AndImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printMemSplsOperand(const MCInst *MI, int OpNo, raw_ostream &O, const char *Modifier=nullptr)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printCCOperand(const MCInst *MI, int OpNo, raw_ostream &O)
void printLo16AndImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printHi16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier=nullptr)
void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O)
This class is intended to be used as a base class for asm properties and features specific to the tar...
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
format_object< int64_t > formatHex(int64_t Value) const
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Instances of this class represent a single low-level machine instruction.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
std::string lower() const
This class implements an extremely fast bulk output stream that can only output to a stream.
static bool isPreOp(unsigned AluOp)
static const char * lanaiAluCodeToString(unsigned AluOp)
static unsigned encodeLanaiAluCode(unsigned AluOp)
static bool isPostOp(unsigned AluOp)
This is an optimization pass for GlobalISel generic memory operations.