31#define DEBUG_TYPE "m68k-expand-pseudo"
32#define PASS_NAME "M68k pseudo instruction expansion pass"
57 MachineFunctionProperties::Property::NoVRegs);
64char M68kExpandPseudo::ID = 0;
76 unsigned Opcode =
MI.getOpcode();
84 return TII->ExpandMOVI(MIB, MVT::i8);
86 return TII->ExpandMOVI(MIB, MVT::i16);
88 return TII->ExpandMOVI(MIB, MVT::i32);
91 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8);
93 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8);
94 case M68k::MOVXd32d16:
95 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16);
97 case M68k::MOVSXd16d8:
98 return TII->ExpandMOVSZX_RR(MIB,
true, MVT::i16, MVT::i8);
99 case M68k::MOVSXd32d8:
100 return TII->ExpandMOVSZX_RR(MIB,
true, MVT::i32, MVT::i8);
101 case M68k::MOVSXd32d16:
102 return TII->ExpandMOVSZX_RR(MIB,
true, MVT::i32, MVT::i16);
104 case M68k::MOVZXd16d8:
105 return TII->ExpandMOVSZX_RR(MIB,
false, MVT::i16, MVT::i8);
106 case M68k::MOVZXd32d8:
107 return TII->ExpandMOVSZX_RR(MIB,
false, MVT::i32, MVT::i8);
108 case M68k::MOVZXd32d16:
109 return TII->ExpandMOVSZX_RR(MIB,
false, MVT::i32, MVT::i16);
111 case M68k::MOVSXd16j8:
112 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dj), MVT::i16,
114 case M68k::MOVSXd32j8:
115 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dj), MVT::i32,
117 case M68k::MOVSXd32j16:
118 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16rj), MVT::i32,
121 case M68k::MOVZXd16j8:
122 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dj), MVT::i16,
124 case M68k::MOVZXd32j8:
125 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dj), MVT::i32,
127 case M68k::MOVZXd32j16:
128 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16rj), MVT::i32,
131 case M68k::MOVSXd16p8:
132 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dp), MVT::i16,
134 case M68k::MOVSXd32p8:
135 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dp), MVT::i32,
137 case M68k::MOVSXd32p16:
138 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16rp), MVT::i32,
141 case M68k::MOVZXd16p8:
142 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dp), MVT::i16,
144 case M68k::MOVZXd32p8:
145 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dp), MVT::i32,
147 case M68k::MOVZXd32p16:
148 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16rp), MVT::i32,
151 case M68k::MOVSXd16f8:
152 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8df), MVT::i16,
154 case M68k::MOVSXd32f8:
155 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8df), MVT::i32,
157 case M68k::MOVSXd32f16:
158 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16rf), MVT::i32,
161 case M68k::MOVZXd16f8:
162 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8df), MVT::i16,
164 case M68k::MOVZXd32f8:
165 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8df), MVT::i32,
167 case M68k::MOVZXd32f16:
168 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16rf), MVT::i32,
171 case M68k::MOVSXd16q8:
172 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dq), MVT::i16,
174 case M68k::MOVSXd32q8:
175 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dq), MVT::i32,
177 case M68k::MOVSXd32q16:
178 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16dq), MVT::i32,
181 case M68k::MOVZXd16q8:
182 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dq), MVT::i16,
184 case M68k::MOVZXd32q8:
185 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dq), MVT::i32,
187 case M68k::MOVZXd32q16:
188 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16dq), MVT::i32,
192 return TII->ExpandCCR(MIB,
true);
194 return TII->ExpandCCR(MIB,
false);
196 case M68k::MOVM8jm_P:
197 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32jm),
false);
198 case M68k::MOVM16jm_P:
199 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32jm),
false);
200 case M68k::MOVM32jm_P:
201 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32jm),
false);
203 case M68k::MOVM8pm_P:
204 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32pm),
false);
205 case M68k::MOVM16pm_P:
206 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32pm),
false);
207 case M68k::MOVM32pm_P:
208 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32pm),
false);
210 case M68k::MOVM8mj_P:
211 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mj),
true);
212 case M68k::MOVM16mj_P:
213 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mj),
true);
214 case M68k::MOVM32mj_P:
215 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mj),
true);
217 case M68k::MOVM8mp_P:
218 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mp),
true);
219 case M68k::MOVM16mp_P:
220 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mp),
true);
221 case M68k::MOVM32mp_P:
222 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mp),
true);
224 case M68k::TCRETURNq:
225 case M68k::TCRETURNj: {
228 assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
231 int StackAdj = StackAdjust.
getImm();
232 int MaxTCDelta = MFI->getTCReturnAddrDelta();
234 assert(MaxTCDelta <= 0 &&
"MaxTCDelta should never be positive");
237 Offset = StackAdj - MaxTCDelta;
238 assert(
Offset >= 0 &&
"Offset should never be negative");
247 if (Opcode == M68k::TCRETURNq) {
275 }
else if (int64_t StackAdj =
MBBI->getOperand(0).getImm(); StackAdj == 0) {
284 FL->emitSPUpdate(
MBB,
MBBI, StackAdj,
true);
321 TII = STI->getInstrInfo();
322 TRI = STI->getRegisterInfo();
324 FL = STI->getFrameLowering();
334 return new M68kExpandPseudo();
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
const HexagonInstrInfo * TII
This file contains the M68k declaration of TargetFrameLowering class.
This file contains the M68k implementation of the TargetInstrInfo class.
This file declares the M68k specific subclass of MachineFunctionInfo.
This file declares the M68k specific subclass of TargetSubtargetInfo.
This file contains the entry points for global functions defined in the M68k target library,...
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
int64_t getOffset() const
Return the offset from the symbol in this operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ M68k_INTR
Used for M68k interrupt routines.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
FunctionPass * createM68kExpandPseudoPass()
Return a Machine IR pass that expands M68k-specific pseudo instructions into a sequence of actual ins...