13#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
46 std::vector<SDValue> &OutOps)
override;
60 template <
unsigned MaxShift>
66 template <
unsigned MaxShift,
unsigned Bits>
71 auto *
C = dyn_cast<ConstantSDNode>(
Index.getOperand(1));
72 if (
C &&
C->getZExtValue() == maskTrailingOnes<uint64_t>(Bits)) {
123 const unsigned Depth = 0)
const;
151 const SDLoc &
DL,
unsigned CurOp,
152 bool IsMasked,
bool IsStridedOrIndexed,
154 bool IsLoad =
false,
MVT *IndexVT =
nullptr);
189#include "RISCVGenDAGISel.inc"
194 bool doPeepholeMergeVVMFold();
195 bool doPeepholeNoRegPassThru();
196 bool performCombineVMergeAndVOps(
SDNode *
N);
272#define GET_RISCVVSSEGTable_DECL
273#define GET_RISCVVLSEGTable_DECL
274#define GET_RISCVVLXSEGTable_DECL
275#define GET_RISCVVSXSEGTable_DECL
276#define GET_RISCVVLETable_DECL
277#define GET_RISCVVSETable_DECL
278#define GET_RISCVVLXTable_DECL
279#define GET_RISCVVSXTable_DECL
amdgpu AMDGPU Register Bank Select
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
mir Rename Register Operands
This class represents an Operation in the Expression.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)
RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with ...
bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, SDValue &Val)
bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
bool hasAllNBitUsers(SDNode *Node, unsigned Bits, const unsigned Depth=0) const
bool SelectAddrRegImmINX(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectVSplatUimmBits(SDValue N, SDValue &Val)
void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset)
Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset shoule be all zeros.
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
bool SelectAddrRegReg(SDValue Addr, SDValue &Base, SDValue &Offset)
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectSETEQ(SDValue N, SDValue &Val)
void selectVLSEGFF(SDNode *Node, bool IsMasked)
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel)
bool selectFPImm(SDValue N, SDValue &Imm)
bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2)
void selectSF_VC_X_SE(SDNode *Node)
bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal)
bool hasAllHUsers(SDNode *Node) const
bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)
bool hasAllWUsers(SDNode *Node) const
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
bool runOnMachineFunction(MachineFunction &MF) override
bool selectSExtBits(SDValue N, SDValue &Val)
RISCVDAGToDAGISel()=delete
bool selectVSplat(SDValue N, SDValue &SplatVal)
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
bool hasAllBUsers(SDNode *Node) const
void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool tryShrinkShlLogicImm(SDNode *Node)
bool selectSETNE(SDValue N, SDValue &Val)
bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
void selectVSETVLI(SDNode *Node)
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
bool selectVLOp(SDValue N, SDValue &VL)
bool trySignedBitfieldExtract(SDNode *Node)
void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, SDValue &Imm)
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset, bool IsINX=false)
bool selectSHXADDOp(SDValue N, SDValue &Val)
void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool selectZExtBits(SDValue N, SDValue &Val)
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
bool tryIndexedLoad(SDNode *Node)
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
virtual bool runOnMachineFunction(MachineFunction &mf)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Primary interface to the complete machine description for the target machine.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ AND
Bitwise operators - logical and, logical or, logical xor.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
This is an optimization pass for GlobalISel generic memory operations.
CodeGenOptLevel
Code generation optimization level.