llvm::RISCVDAGToDAGISel Class Reference

#include "Target/RISCV/RISCVISelDAGToDAG.h"

Inheritance diagram for llvm::RISCVDAGToDAGISel:

Public Member Functions
	RISCVDAGToDAGISel ()=delete
	RISCVDAGToDAGISel (RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel)
bool	runOnMachineFunction (MachineFunction &MF) override
void	PreprocessISelDAG () override
	PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
void	PostprocessISelDAG () override
	PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
void	Select (SDNode *Node) override
	Main hook for targets to transform nodes into machine nodes.
bool	SelectInlineAsmMemoryOperand (const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
	SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
bool	SelectAddrFrameIndex (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	SelectFrameAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	SelectAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset, bool IsINX=false)
bool	SelectAddrRegImmINX (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	SelectAddrRegImmLsb00000 (SDValue Addr, SDValue &Base, SDValue &Offset)
	Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset shoule be all zeros.
bool	SelectAddrRegRegScale (SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)
template<unsigned MaxShift>
bool	SelectAddrRegRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
template<unsigned MaxShift, unsigned Bits>
bool	SelectAddrRegZextRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool	SelectAddrRegReg (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	tryShrinkShlLogicImm (SDNode *Node)
bool	trySignedBitfieldExtract (SDNode *Node)
bool	tryIndexedLoad (SDNode *Node)
bool	selectShiftMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool	selectShiftMaskXLen (SDValue N, SDValue &ShAmt)
bool	selectShiftMask32 (SDValue N, SDValue &ShAmt)
bool	selectSETCC (SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)
	RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0.
bool	selectSETNE (SDValue N, SDValue &Val)
bool	selectSETEQ (SDValue N, SDValue &Val)
bool	selectSExtBits (SDValue N, unsigned Bits, SDValue &Val)
template<unsigned Bits>
bool	selectSExtBits (SDValue N, SDValue &Val)
bool	selectZExtBits (SDValue N, unsigned Bits, SDValue &Val)
template<unsigned Bits>
bool	selectZExtBits (SDValue N, SDValue &Val)
bool	selectSHXADDOp (SDValue N, unsigned ShAmt, SDValue &Val)
	Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
template<unsigned ShAmt>
bool	selectSHXADDOp (SDValue N, SDValue &Val)
bool	selectSHXADD_UWOp (SDValue N, unsigned ShAmt, SDValue &Val)
	Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
template<unsigned ShAmt>
bool	selectSHXADD_UWOp (SDValue N, SDValue &Val)
bool	hasAllNBitUsers (SDNode *Node, unsigned Bits, const unsigned Depth=0) const
bool	hasAllBUsers (SDNode *Node) const
bool	hasAllHUsers (SDNode *Node) const
bool	hasAllWUsers (SDNode *Node) const
bool	selectSimm5Shl2 (SDValue N, SDValue &Simm5, SDValue &Shl2)
bool	selectVLOp (SDValue N, SDValue &VL)
bool	selectVSplat (SDValue N, SDValue &SplatVal)
bool	selectVSplatSimm5 (SDValue N, SDValue &SplatVal)
bool	selectVSplatUimm (SDValue N, unsigned Bits, SDValue &SplatVal)
template<unsigned Bits>
bool	selectVSplatUimmBits (SDValue N, SDValue &Val)
bool	selectVSplatSimm5Plus1 (SDValue N, SDValue &SplatVal)
bool	selectVSplatSimm5Plus1NonZero (SDValue N, SDValue &SplatVal)
bool	selectLow8BitsVSplat (SDValue N, SDValue &SplatVal)
bool	selectFPImm (SDValue N, SDValue &Imm)
bool	selectRVVSimm5 (SDValue N, unsigned Width, SDValue &Imm)
template<unsigned Width>
bool	selectRVVSimm5 (SDValue N, SDValue &Imm)
void	addVectorLoadStoreOperands (SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
void	selectVLSEG (SDNode *Node, bool IsMasked, bool IsStrided)
void	selectVLSEGFF (SDNode *Node, bool IsMasked)
void	selectVLXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)
void	selectVSSEG (SDNode *Node, bool IsMasked, bool IsStrided)
void	selectVSXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)
void	selectVSETVLI (SDNode *Node)
void	selectSF_VC_X_SE (SDNode *Node)
Public Member Functions inherited from llvm::SelectionDAGISel
	SelectionDAGISel (TargetMachine &tm, CodeGenOptLevel OL=CodeGenOptLevel::Default)
virtual	~SelectionDAGISel ()
const TargetLowering *	getTargetLowering () const
void	initializeAnalysisResults (MachineFunctionAnalysisManager &MFAM)
void	initializeAnalysisResults (MachineFunctionPass &MFP)
virtual bool	runOnMachineFunction (MachineFunction &mf)
virtual void	emitFunctionEntryCode ()
virtual void	PreprocessISelDAG ()
	PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
virtual void	PostprocessISelDAG ()
	PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
virtual void	Select (SDNode *N)=0
	Main hook for targets to transform nodes into machine nodes.
virtual bool	SelectInlineAsmMemoryOperand (const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps)
	SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
virtual bool	IsProfitableToFold (SDValue N, SDNode *U, SDNode *Root) const
	IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root.
bool	CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckAndMask - The isel is trying to match something like (and X, 255).
bool	CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckOrMask - The isel is trying to match something like (or X, 255).
virtual bool	CheckPatternPredicate (unsigned PredNo) const
	CheckPatternPredicate - This function is generated by tblgen in the target.
virtual bool	CheckNodePredicate (SDNode *N, unsigned PredNo) const
	CheckNodePredicate - This function is generated by tblgen in the target.
virtual bool	CheckNodePredicateWithOperands (SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
	CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
virtual bool	CheckComplexPattern (SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
virtual SDValue	RunSDNodeXForm (SDValue V, unsigned XFormNo)
void	SelectCodeCommon (SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
virtual bool	ComplexPatternFuncMutatesDAG () const
	Return true if complex patterns for this target can mutate the DAG.
bool	mayRaiseFPException (SDNode *Node) const
	Return whether the node may raise an FP exception.
bool	isOrEquivalentToAdd (const SDNode *N) const

Static Public Member Functions
static RISCVCC::CondCode	getRISCVCCForIntCC (ISD::CondCode CC)
Static Public Member Functions inherited from llvm::SelectionDAGISel
static bool	IsLegalToFold (SDValue N, SDNode *U, SDNode *Root, CodeGenOptLevel OptLevel, bool IgnoreChains=false)
	IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root.
static void	InvalidateNodeId (SDNode *N)
static int	getUninvalidatedNodeId (SDNode *N)
static void	EnforceNodeIdInvariant (SDNode *N)
static int	getNumFixedFromVariadicInfo (unsigned Flags)
	getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root.

Additional Inherited Members
Public Types inherited from llvm::SelectionDAGISel
enum	BuiltinOpcodes {   OPC_Scope , OPC_RecordNode , OPC_RecordChild0 , OPC_RecordChild1 ,   OPC_RecordChild2 , OPC_RecordChild3 , OPC_RecordChild4 , OPC_RecordChild5 ,   OPC_RecordChild6 , OPC_RecordChild7 , OPC_RecordMemRef , OPC_CaptureGlueInput ,   OPC_MoveChild , OPC_MoveChild0 , OPC_MoveChild1 , OPC_MoveChild2 ,   OPC_MoveChild3 , OPC_MoveChild4 , OPC_MoveChild5 , OPC_MoveChild6 ,   OPC_MoveChild7 , OPC_MoveSibling , OPC_MoveSibling0 , OPC_MoveSibling1 ,   OPC_MoveSibling2 , OPC_MoveSibling3 , OPC_MoveSibling4 , OPC_MoveSibling5 ,   OPC_MoveSibling6 , OPC_MoveSibling7 , OPC_MoveParent , OPC_CheckSame ,   OPC_CheckChild0Same , OPC_CheckChild1Same , OPC_CheckChild2Same , OPC_CheckChild3Same ,   OPC_CheckPatternPredicate , OPC_CheckPatternPredicate0 , OPC_CheckPatternPredicate1 , OPC_CheckPatternPredicate2 ,   OPC_CheckPatternPredicate3 , OPC_CheckPatternPredicate4 , OPC_CheckPatternPredicate5 , OPC_CheckPatternPredicate6 ,   OPC_CheckPatternPredicate7 , OPC_CheckPatternPredicateTwoByte , OPC_CheckPredicate , OPC_CheckPredicate0 ,   OPC_CheckPredicate1 , OPC_CheckPredicate2 , OPC_CheckPredicate3 , OPC_CheckPredicate4 ,   OPC_CheckPredicate5 , OPC_CheckPredicate6 , OPC_CheckPredicate7 , OPC_CheckPredicateWithOperands ,   OPC_CheckOpcode , OPC_SwitchOpcode , OPC_CheckType , OPC_CheckTypeI32 ,   OPC_CheckTypeI64 , OPC_CheckTypeRes , OPC_SwitchType , OPC_CheckChild0Type ,   OPC_CheckChild1Type , OPC_CheckChild2Type , OPC_CheckChild3Type , OPC_CheckChild4Type ,   OPC_CheckChild5Type , OPC_CheckChild6Type , OPC_CheckChild7Type , OPC_CheckChild0TypeI32 ,   OPC_CheckChild1TypeI32 , OPC_CheckChild2TypeI32 , OPC_CheckChild3TypeI32 , OPC_CheckChild4TypeI32 ,   OPC_CheckChild5TypeI32 , OPC_CheckChild6TypeI32 , OPC_CheckChild7TypeI32 , OPC_CheckChild0TypeI64 ,   OPC_CheckChild1TypeI64 , OPC_CheckChild2TypeI64 , OPC_CheckChild3TypeI64 , OPC_CheckChild4TypeI64 ,   OPC_CheckChild5TypeI64 , OPC_CheckChild6TypeI64 , OPC_CheckChild7TypeI64 , OPC_CheckInteger ,   OPC_CheckChild0Integer , OPC_CheckChild1Integer , OPC_CheckChild2Integer , OPC_CheckChild3Integer ,   OPC_CheckChild4Integer , OPC_CheckCondCode , OPC_CheckChild2CondCode , OPC_CheckValueType ,   OPC_CheckComplexPat , OPC_CheckComplexPat0 , OPC_CheckComplexPat1 , OPC_CheckComplexPat2 ,   OPC_CheckComplexPat3 , OPC_CheckComplexPat4 , OPC_CheckComplexPat5 , OPC_CheckComplexPat6 ,   OPC_CheckComplexPat7 , OPC_CheckAndImm , OPC_CheckOrImm , OPC_CheckImmAllOnesV ,   OPC_CheckImmAllZerosV , OPC_CheckFoldableChainNode , OPC_EmitInteger , OPC_EmitInteger8 ,   OPC_EmitInteger16 , OPC_EmitInteger32 , OPC_EmitInteger64 , OPC_EmitStringInteger ,   OPC_EmitStringInteger32 , OPC_EmitRegister , OPC_EmitRegisterI32 , OPC_EmitRegisterI64 ,   OPC_EmitRegister2 , OPC_EmitConvertToTarget , OPC_EmitConvertToTarget0 , OPC_EmitConvertToTarget1 ,   OPC_EmitConvertToTarget2 , OPC_EmitConvertToTarget3 , OPC_EmitConvertToTarget4 , OPC_EmitConvertToTarget5 ,   OPC_EmitConvertToTarget6 , OPC_EmitConvertToTarget7 , OPC_EmitMergeInputChains , OPC_EmitMergeInputChains1_0 ,   OPC_EmitMergeInputChains1_1 , OPC_EmitMergeInputChains1_2 , OPC_EmitCopyToReg , OPC_EmitCopyToReg0 ,   OPC_EmitCopyToReg1 , OPC_EmitCopyToReg2 , OPC_EmitCopyToReg3 , OPC_EmitCopyToReg4 ,   OPC_EmitCopyToReg5 , OPC_EmitCopyToReg6 , OPC_EmitCopyToReg7 , OPC_EmitCopyToRegTwoByte ,   OPC_EmitNodeXForm , OPC_EmitNode , OPC_EmitNode0 , OPC_EmitNode1 ,   OPC_EmitNode2 , OPC_EmitNode0None , OPC_EmitNode1None , OPC_EmitNode2None ,   OPC_EmitNode0Chain , OPC_EmitNode1Chain , OPC_EmitNode2Chain , OPC_MorphNodeTo ,   OPC_MorphNodeTo0 , OPC_MorphNodeTo1 , OPC_MorphNodeTo2 , OPC_MorphNodeTo0None ,   OPC_MorphNodeTo1None , OPC_MorphNodeTo2None , OPC_MorphNodeTo0Chain , OPC_MorphNodeTo1Chain ,   OPC_MorphNodeTo2Chain , OPC_MorphNodeTo0GlueInput , OPC_MorphNodeTo1GlueInput , OPC_MorphNodeTo2GlueInput ,   OPC_MorphNodeTo0GlueOutput , OPC_MorphNodeTo1GlueOutput , OPC_MorphNodeTo2GlueOutput , OPC_CompleteMatch ,   OPC_Coverage }
enum	{   OPFL_None = 0 , OPFL_Chain = 1 , OPFL_GlueInput = 2 , OPFL_GlueOutput = 4 ,   OPFL_MemRefs = 8 , OPFL_Variadic0 = 1<<4 , OPFL_Variadic1 = 2<<4 , OPFL_Variadic2 = 3<<4 ,   OPFL_Variadic3 = 4<<4 , OPFL_Variadic4 = 5<<4 , OPFL_Variadic5 = 6<<4 , OPFL_Variadic6 = 7<<4 ,   OPFL_VariadicInfo = OPFL_Variadic6 }
Public Attributes inherited from llvm::SelectionDAGISel
TargetMachine &	TM
const TargetLibraryInfo *	LibInfo
std::unique_ptr< FunctionLoweringInfo >	FuncInfo
SwiftErrorValueTracking *	SwiftError
MachineFunction *	MF
MachineModuleInfo *	MMI
MachineRegisterInfo *	RegInfo
SelectionDAG *	CurDAG
std::unique_ptr< SelectionDAGBuilder >	SDB
AAResults *	AA = nullptr
AssumptionCache *	AC = nullptr
GCFunctionInfo *	GFI = nullptr
SSPLayoutInfo *	SP = nullptr
CodeGenOptLevel	OptLevel
const TargetInstrInfo *	TII
const TargetLowering *	TLI
bool	FastISelFailed
SmallPtrSet< const Instruction *, 4 >	ElidedArgCopyInstrs
std::unique_ptr< OptimizationRemarkEmitter >	ORE
	Current optimization remark emitter.
bool	MatchFilterFuncName = false
	True if the function currently processing is in the function printing list (i.e.
StringRef	FuncName
Protected Member Functions inherited from llvm::SelectionDAGISel
void	ReplaceUses (SDValue F, SDValue T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T.
void	ReplaceUses (const SDValue *F, const SDValue *T, unsigned Num)
	ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
void	ReplaceUses (SDNode *F, SDNode *T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T.
void	ReplaceNode (SDNode *F, SDNode *T)
	Replace all uses of F with T, then remove F from the DAG.
void	SelectInlineAsmMemoryOperands (std::vector< SDValue > &Ops, const SDLoc &DL)
	SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
virtual StringRef	getPatternForIndex (unsigned index)
	getPatternForIndex - Patterns selected by tablegen during ISEL
virtual StringRef	getIncludePathForIndex (unsigned index)
	getIncludePathForIndex - get the td source location of pattern instantiation
bool	shouldOptForSize (const MachineFunction *MF) const
Protected Attributes inherited from llvm::SelectionDAGISel
unsigned	DAGSize = 0
	DAGSize - Size of DAG being instruction selected.

Detailed Description

Definition at line 24 of file RISCVISelDAGToDAG.h.

Constructor & Destructor Documentation

RISCVDAGToDAGISel() [1/2]

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel ( )

delete

RISCVDAGToDAGISel() [2/2]

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel ( RISCVTargetMachine &  TargetMachine, CodeGenOptLevel  OptLevel  )

inlineexplicit

Definition at line 30 of file RISCVISelDAGToDAG.h.

Member Function Documentation

addVectorLoadStoreOperands()

void RISCVDAGToDAGISel::addVectorLoadStoreOperands	(	SDNode *	Node,
		unsigned	SEWImm,
		const SDLoc &	DL,
		unsigned	CurOp,
		bool	IsMasked,
		bool	IsStridedOrIndexed,
		SmallVectorImpl< SDValue > &	Operands,
		bool	IsLoad = false,
		MVT *	IndexVT = nullptr
	)

Definition at line 295 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVII::MASK_AGNOSTIC, Operands, and selectVLOp().

Referenced by Select(), selectVLSEG(), selectVLSEGFF(), selectVLXSEG(), selectVSSEG(), and selectVSXSEG().

getRISCVCCForIntCC()

static RISCVCC::CondCode llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC ( ISD::CondCode  CC )

inlinestatic

Definition at line 169 of file RISCVISelDAGToDAG.h.

References CC, llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, and llvm::ISD::SETULT.

hasAllBUsers()

bool llvm::RISCVDAGToDAGISel::hasAllBUsers ( SDNode *  Node ) const

inline

Definition at line 124 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

hasAllHUsers()

bool llvm::RISCVDAGToDAGISel::hasAllHUsers ( SDNode *  Node ) const

inline

Definition at line 125 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

hasAllNBitUsers()

bool RISCVDAGToDAGISel::hasAllNBitUsers	(	SDNode *	Node,
		unsigned	Bits,
		const unsigned	Depth = 0
	)		const

Definition at line 3203 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::bit_width(), llvm::Depth, llvm::User::getOperand(), llvm::RISCVSubtarget::getXLen(), hasAllNBitUsers(), llvm::Log2_32(), llvm::SelectionDAG::MaxRecursionDepth, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRL, llvm::ISD::SUB, llvm::SelectionDAGISel::TII, vectorPseudoHasAllNBitUsers(), and llvm::ISD::XOR.

Referenced by hasAllBUsers(), hasAllHUsers(), hasAllNBitUsers(), and hasAllWUsers().

hasAllWUsers()

bool llvm::RISCVDAGToDAGISel::hasAllWUsers ( SDNode *  Node ) const

inline

Definition at line 126 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

PostprocessISelDAG()

void RISCVDAGToDAGISel::PostprocessISelDAG ( )

overridevirtual

PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 141 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getRoot(), N, llvm::SelectionDAG::RemoveDeadNodes(), and llvm::SelectionDAG::setRoot().

PreprocessISelDAG()

void RISCVDAGToDAGISel::PreprocessISelDAG ( )

overridevirtual

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 50 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), llvm::ISD::ANY_EXTEND, assert(), llvm::SelectionDAG::CreateStackTemporary(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), DL, llvm::SelectionDAG::getEntryNode(), llvm::TypeSize::getFixed(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MachinePointerInfo::getWithOffset(), llvm::RISCVSubtarget::getXLenVT(), llvm::Hi, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), LLVM_DEBUG, llvm::Lo, llvm::SelectionDAGISel::MF, llvm::MachineMemOperand::MOLoad, N, llvm::SelectionDAG::RemoveDeadNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SPLAT_VECTOR, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, llvm::ISD::TokenFactor, llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VMV_V_X_VL.

runOnMachineFunction()

bool llvm::RISCVDAGToDAGISel::runOnMachineFunction ( MachineFunction &  MF )

inlineoverridevirtual

Reimplemented from llvm::SelectionDAGISel.

Definition at line 34 of file RISCVISelDAGToDAG.h.

References llvm::MachineFunction::getSubtarget(), llvm::SelectionDAGISel::MF, and llvm::SelectionDAGISel::runOnMachineFunction().

Select()

void RISCVDAGToDAGISel::Select ( SDNode *  N )

overridevirtual

Main hook for targets to transform nodes into machine nodes.

Implements llvm::SelectionDAGISel.

Definition at line 880 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), llvm::ISD::AND, assert(), llvm::sampleprof::Base, llvm::bit_width(), llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), llvm::RISCVISD::BuildPairF64, llvm::CallingConv::C, CASE_VMSLT_OPCODES, CASE_VMSLT_VMNAND_VMSET_OPCODES, CASE_VMXOR_VMANDN_VMOR_OPCODES, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::countr_one(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), DL, llvm::RISCVSubtarget::expandVScale(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetMachine::getOptLevel(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::TypeSize::getScalable(), llvm::MVT::getScalarSizeInBits(), llvm::APInt::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::EVT::getStoreSize(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getTargetInsertSubreg(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), hasAllBUsers(), hasAllHUsers(), hasAllWUsers(), llvm::SDValue::hasOneUse(), llvm::Hi, Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::RISCVSubtarget::is64Bit(), llvm::MVT::isFixedLengthVector(), llvm::SelectionDAGISel::IsLegalToFold(), llvm::isMask_64(), llvm::APFloat::isNegZero(), llvm::isOneConstant(), llvm::APFloat::isPosZero(), llvm::isPowerOf2_64(), llvm::SelectionDAGISel::IsProfitableToFold(), llvm::MVT::isScalableVector(), llvm::isShiftedMask_64(), llvm::APFloat::isZero(), LLVM_DEBUG, llvm_unreachable, llvm::RISCVII::LMUL_F2, llvm::RISCVII::LMUL_F4, llvm::RISCVII::LMUL_F8, llvm::Lo, llvm::ISD::LOAD, llvm::Log2_32(), llvm::M1(), llvm::RISCVII::MASK_AGNOSTIC, llvm::MachineMemOperand::MONonTemporal, llvm::MONontemporalBit0, llvm::MONontemporalBit1, llvm::ISD::MUL, N, llvm::Offset, Operands, llvm::ISD::OR, P, llvm::ISD::POST_INC, llvm::ISD::PREFETCH, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAGISel::ReplaceUses(), llvm::report_fatal_error(), llvm::RISCVFPRndMode::RNE, llvm::RISCV::RVVBitsPerBlock, selectImm(), selectSF_VC_X_SE(), selectVLOp(), selectVLSEG(), selectVLSEGFF(), selectVLXSEG(), selectVSETVLI(), selectVSSEG(), selectVSXSEG(), llvm::MachineMemOperand::setFlags(), llvm::SelectionDAG::setNodeMemRefs(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::SimpleTy, llvm::RISCVISD::SplitF64, llvm::ISD::SRA, llvm::ISD::SRL, llvm::RISCVII::TAIL_AGNOSTIC, llvm::SelectionDAGISel::TLI, llvm::SelectionDAGISel::TM, TRI, tryIndexedLoad(), tryShrinkShlLogicImm(), trySignedBitfieldExtract(), llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_S_X_VL, llvm::RISCVISD::VMV_V_X_VL, X, and llvm::ISD::XOR.

SelectAddrFrameIndex()

bool RISCVDAGToDAGISel::SelectAddrFrameIndex	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset
	)

Definition at line 2487 of file RISCVISelDAGToDAG.cpp.

References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), and llvm::Offset.

Referenced by SelectAddrRegImm(), SelectAddrRegImmLsb00000(), and SelectFrameAddrRegImm().

SelectAddrRegImm()

bool RISCVDAGToDAGISel::SelectAddrRegImm	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset,
		bool	IsINX = false
	)

Definition at line 2651 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::RISCVISD::ADD_LO, Addr, assert(), llvm::sampleprof::Base, llvm::commonAlignment(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValueType(), llvm::SelectionDAG::isBaseWithConstantOffset(), isWorthFoldingAdd(), llvm::Offset, SelectAddrFrameIndex(), and selectConstantAddr().

Referenced by SelectAddrRegImmINX(), and SelectInlineAsmMemoryOperand().

SelectAddrRegImmINX()

bool llvm::RISCVDAGToDAGISel::SelectAddrRegImmINX ( SDValue  Addr, SDValue &  Base, SDValue &  Offset  )

inline

Definition at line 52 of file RISCVISelDAGToDAG.h.

References Addr, llvm::sampleprof::Base, llvm::Offset, and SelectAddrRegImm().

SelectAddrRegImmLsb00000()

bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset
	)

Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset shoule be all zeros.

Definition at line 2746 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, Addr, assert(), llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::Offset, SelectAddrFrameIndex(), and selectConstantAddr().

SelectAddrRegReg()

bool RISCVDAGToDAGISel::SelectAddrRegReg	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset
	)

Definition at line 2811 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, Addr, llvm::sampleprof::Base, and llvm::Offset.

SelectAddrRegRegScale() [1/2]

template<unsigned MaxShift>

bool llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale ( SDValue  Addr, SDValue &  Base, SDValue &  Index, SDValue &  Scale  )

inline

Definition at line 61 of file RISCVISelDAGToDAG.h.

References Addr, llvm::sampleprof::Base, and SelectAddrRegRegScale().

SelectAddrRegRegScale() [2/2]

bool RISCVDAGToDAGISel::SelectAddrRegRegScale	(	SDValue	Addr,
		unsigned	MaxShiftAmount,
		SDValue &	Base,
		SDValue &	Index,
		SDValue &	Scale
	)

Definition at line 2597 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::ISD::SHL.

Referenced by SelectAddrRegRegScale(), and SelectAddrRegZextRegScale().

SelectAddrRegZextRegScale()

template<unsigned MaxShift, unsigned Bits>

bool llvm::RISCVDAGToDAGISel::SelectAddrRegZextRegScale ( SDValue  Addr, SDValue &  Base, SDValue &  Index, SDValue &  Scale  )

inline

Definition at line 67 of file RISCVISelDAGToDAG.h.

References Addr, llvm::ISD::AND, llvm::sampleprof::Base, llvm::CallingConv::C, and SelectAddrRegRegScale().

selectFPImm()

bool RISCVDAGToDAGISel::selectFPImm	(	SDValue	N,
		SDValue &	Imm
	)

Definition at line 3523 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::APFloat::bitcastToAPInt(), llvm::SelectionDAGISel::CurDAG, DL, llvm::APInt::getSExtValue(), llvm::SDNode::getSimpleValueType(), llvm::ConstantFPSDNode::getValueAPF(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::is64Bit(), llvm::APFloat::isNegZero(), llvm::APFloat::isPosZero(), N, selectImm(), and llvm::SelectionDAGISel::TLI.

SelectFrameAddrRegImm()

bool RISCVDAGToDAGISel::SelectFrameAddrRegImm	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset
	)

Definition at line 2499 of file RISCVISelDAGToDAG.cpp.

References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::Offset, and SelectAddrFrameIndex().

SelectInlineAsmMemoryOperand()

bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand ( const SDValue &  Op, InlineAsm::ConstraintCode  ConstraintID, std::vector< SDValue > &  OutOps  )

overridevirtual

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.

If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 2459 of file RISCVISelDAGToDAG.cpp.

References llvm::InlineAsm::A, assert(), llvm::SelectionDAGISel::CurDAG, llvm::InlineAsm::getMemConstraintName(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::InlineAsm::m, llvm::InlineAsm::o, llvm::report_fatal_error(), and SelectAddrRegImm().

selectLow8BitsVSplat()

bool RISCVDAGToDAGISel::selectLow8BitsVSplat	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 3497 of file RISCVISelDAGToDAG.cpp.

References N, selectVSplat(), llvm::ISD::SIGN_EXTEND, llvm::RISCVISD::TRUNCATE_VECTOR_VL, llvm::RISCVISD::VSEXT_VL, llvm::RISCVISD::VZEXT_VL, and llvm::ISD::ZERO_EXTEND.

selectRVVSimm5() [1/2]

template<unsigned Width>

bool llvm::RISCVDAGToDAGISel::selectRVVSimm5 ( SDValue  N, SDValue &  Imm  )

inline

Definition at line 146 of file RISCVISelDAGToDAG.h.

References N, and selectRVVSimm5().

selectRVVSimm5() [2/2]

bool RISCVDAGToDAGISel::selectRVVSimm5	(	SDValue	N,
		unsigned	Width,
		SDValue &	Imm
	)

Definition at line 3553 of file RISCVISelDAGToDAG.cpp.

References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getSignedConstant(), llvm::RISCVSubtarget::getXLenVT(), N, and llvm::SignExtend64().

Referenced by selectRVVSimm5().

selectSETCC()

bool RISCVDAGToDAGISel::selectSETCC	(	SDValue	N,
		ISD::CondCode	ExpectedCCVal,
		SDValue &	Val
	)

RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0.

This function emits instructions that convert the seteq/setne into something that can be compared with 0. ExpectedCCVal indicates the condition code to attempt to match (e.g. ISD::SETNE).

Definition at line 2901 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getSignedConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), LHS, N, RHS, and llvm::ISD::SETCC.

Referenced by selectSETEQ(), and selectSETNE().

selectSETEQ()

bool llvm::RISCVDAGToDAGISel::selectSETEQ ( SDValue  N, SDValue &  Val  )

inline

Definition at line 99 of file RISCVISelDAGToDAG.h.

References N, selectSETCC(), and llvm::ISD::SETEQ.

selectSETNE()

bool llvm::RISCVDAGToDAGISel::selectSETNE ( SDValue  N, SDValue &  Val  )

inline

Definition at line 96 of file RISCVISelDAGToDAG.h.

References N, selectSETCC(), and llvm::ISD::SETNE.

selectSExtBits() [1/2]

template<unsigned Bits>

bool llvm::RISCVDAGToDAGISel::selectSExtBits ( SDValue  N, SDValue &  Val  )

inline

Definition at line 104 of file RISCVISelDAGToDAG.h.

References N, and selectSExtBits().

selectSExtBits() [2/2]

bool RISCVDAGToDAGISel::selectSExtBits	(	SDValue	N,
		unsigned	Bits,
		SDValue &	Val
	)

Definition at line 2960 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAGISel::CurDAG, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getSizeInBits(), N, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::SRA.

Referenced by selectSExtBits().

selectSF_VC_X_SE()

void RISCVDAGToDAGISel::selectSF_VC_X_SE

(

SDNode *

Node

)

Definition at line 821 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructions(), llvm::ISD::INTRINSIC_VOID, llvm::Log2_32(), Operands, and llvm::SelectionDAGISel::ReplaceNode().

Referenced by Select().

selectShiftMask()

bool RISCVDAGToDAGISel::selectShiftMask	(	SDValue	N,
		unsigned	ShiftWidth,
		SDValue &	ShAmt
	)

Definition at line 2824 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::APInt::getBitWidth(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getValueType(), llvm::isPowerOf2_32(), llvm::APInt::isSubsetOf(), N, llvm::ISD::SUB, llvm::KnownBits::Zero, and llvm::ISD::ZERO_EXTEND.

Referenced by selectShiftMask32(), and selectShiftMaskXLen().

selectShiftMask32()

bool llvm::RISCVDAGToDAGISel::selectShiftMask32 ( SDValue  N, SDValue &  ShAmt  )

inline

Definition at line 91 of file RISCVISelDAGToDAG.h.

References N, and selectShiftMask().

selectShiftMaskXLen()

bool llvm::RISCVDAGToDAGISel::selectShiftMaskXLen ( SDValue  N, SDValue &  ShAmt  )

inline

Definition at line 88 of file RISCVISelDAGToDAG.h.

References llvm::RISCVSubtarget::getXLen(), N, and selectShiftMask().

selectSHXADD_UWOp() [1/2]

template<unsigned ShAmt>

bool llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp ( SDValue  N, SDValue &  Val  )

inline

Definition at line 118 of file RISCVISelDAGToDAG.h.

References N, and selectSHXADD_UWOp().

selectSHXADD_UWOp() [2/2]

bool RISCVDAGToDAGISel::selectSHXADD_UWOp	(	SDValue	N,
		unsigned	ShAmt,
		SDValue &	Val
	)

Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.

ShAmt contains 1, 2, or 3 and is set based on which SHXADD_UW we are trying to match.

Definition at line 3130 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::countl_zero(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), N, and llvm::ISD::SHL.

Referenced by selectSHXADD_UWOp().

selectSHXADDOp() [1/2]

template<unsigned ShAmt>

bool llvm::RISCVDAGToDAGISel::selectSHXADDOp ( SDValue  N, SDValue &  Val  )

inline

Definition at line 113 of file RISCVISelDAGToDAG.h.

References N, and selectSHXADDOp().

selectSHXADDOp() [2/2]

bool RISCVDAGToDAGISel::selectSHXADDOp	(	SDValue	N,
		unsigned	ShAmt,
		SDValue &	Val
	)

Look for various patterns that can be done with a SHL that can be folded into a SHXADD.

ShAmt contains 1, 2, or 3 and is set based on which SHXADD we are trying to match.

Definition at line 3010 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::bit_width(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLen(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), N, llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by selectSHXADDOp().

selectSimm5Shl2()

bool RISCVDAGToDAGISel::selectSimm5Shl2	(	SDValue	N,
		SDValue &	Simm5,
		SDValue &	Shl2
	)

Definition at line 3367 of file RISCVISelDAGToDAG.cpp.

References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::Offset.

selectVLOp()

bool RISCVDAGToDAGISel::selectVLOp	(	SDValue	N,
		SDValue &	VL
	)

Definition at line 3392 of file RISCVISelDAGToDAG.cpp.

References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, getReg(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::RISCV::VLMaxSentinel.

Referenced by addVectorLoadStoreOperands(), and Select().

selectVLSEG()

void RISCVDAGToDAGISel::selectVLSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsStrided
	)

Definition at line 341 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::RISCVTargetLowering::getSubregIndexByMVT(), llvm::SelectionDAG::getTargetExtractSubreg(), I, llvm::Log2_32(), Merge, Operands, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceUses(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectVLSEGFF()

void RISCVDAGToDAGISel::selectVLSEGFF	(	SDNode *	Node,
		bool	IsMasked
	)

Definition at line 381 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::RISCVTargetLowering::getSubregIndexByMVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::Log2_32(), Operands, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceUses(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectVLXSEG()

void RISCVDAGToDAGISel::selectVLXSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsOrdered
	)

Definition at line 423 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), assert(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::RISCVTargetLowering::getSubregIndexByMVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::MVT::getVectorElementCount(), I, llvm::RISCVSubtarget::is64Bit(), llvm::Log2_32(), Operands, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceUses(), llvm::report_fatal_error(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectVSETVLI()

void RISCVDAGToDAGISel::selectVSETVLI

(

SDNode *

Node

)

Definition at line 548 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::RISCVVType::decodeVSEW(), DL, llvm::RISCVVType::encodeVTYPE(), llvm::SelectionDAG::getMachineNode(), llvm::RISCVSubtarget::getRealVLen(), llvm::SelectionDAG::getRegister(), llvm::RISCVVType::getSEWLMULRatio(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructions(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isAllOnesConstant(), llvm::Offset, and llvm::SelectionDAGISel::ReplaceNode().

Referenced by Select().

selectVSplat()

bool RISCVDAGToDAGISel::selectVSplat	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 3431 of file RISCVISelDAGToDAG.cpp.

References findVSplat(), N, and llvm::Splat.

Referenced by selectLow8BitsVSplat().

selectVSplatSimm5()

bool RISCVDAGToDAGISel::selectVSplatSimm5	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 3471 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, N, and selectVSplatImmHelper().

selectVSplatSimm5Plus1()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 3476 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, N, and selectVSplatImmHelper().

selectVSplatSimm5Plus1NonZero()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 3482 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, N, and selectVSplatImmHelper().

selectVSplatUimm()

bool RISCVDAGToDAGISel::selectVSplatUimm	(	SDValue	N,
		unsigned	Bits,
		SDValue &	SplatVal
	)

Definition at line 3490 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, llvm::isUIntN(), N, and selectVSplatImmHelper().

Referenced by selectVSplatUimmBits().

selectVSplatUimmBits()

template<unsigned Bits>

bool llvm::RISCVDAGToDAGISel::selectVSplatUimmBits ( SDValue  N, SDValue &  Val  )

inline

Definition at line 135 of file RISCVISelDAGToDAG.h.

References N, and selectVSplatUimm().

selectVSSEG()

void RISCVDAGToDAGISel::selectVSSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsStrided
	)

Definition at line 474 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::Log2_32(), Operands, P, llvm::SelectionDAGISel::ReplaceNode(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectVSXSEG()

void RISCVDAGToDAGISel::selectVSXSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsOrdered
	)

Definition at line 506 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), assert(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::RISCVSubtarget::is64Bit(), llvm::Log2_32(), Operands, P, llvm::SelectionDAGISel::ReplaceNode(), llvm::report_fatal_error(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectZExtBits() [1/2]

template<unsigned Bits>

bool llvm::RISCVDAGToDAGISel::selectZExtBits ( SDValue  N, SDValue &  Val  )

inline

Definition at line 108 of file RISCVISelDAGToDAG.h.

References N, and selectZExtBits().

selectZExtBits() [2/2]

bool RISCVDAGToDAGISel::selectZExtBits	(	SDValue	N,
		unsigned	Bits,
		SDValue &	Val
	)

Definition at line 2989 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::APInt::getBitsSetFrom(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::MaskedValueIsZero(), and N.

Referenced by selectZExtBits().

tryIndexedLoad()

bool RISCVDAGToDAGISel::tryIndexedLoad

(

SDNode *

Node

)

Definition at line 751 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::LSBaseSDNode::getAddressingMode(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getMachineNode(), llvm::MemSDNode::getMemoryVT(), llvm::LoadSDNode::getOffset(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::Offset, llvm::ISD::POST_INC, llvm::ISD::PRE_INC, llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAG::setNodeMemRefs(), llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.

Referenced by Select().

tryShrinkShlLogicImm()

bool RISCVDAGToDAGISel::tryShrinkShlLogicImm

(

SDNode *

Node

)

Definition at line 606 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, assert(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm_unreachable, llvm::ISD::OR, llvm::SelectionDAGISel::ReplaceNode(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::XOR.

Referenced by Select().

trySignedBitfieldExtract()

bool RISCVDAGToDAGISel::trySignedBitfieldExtract

(

SDNode *

Node

)

Definition at line 684 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::SelectionDAGISel::ReplaceNode(), llvm::ISD::SHL, and llvm::ISD::SIGN_EXTEND_INREG.

Referenced by Select().

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The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVISelDAGToDAG.h
• lib/Target/RISCV/RISCVISelDAGToDAG.cpp