RISCVISelDAGToDAG.cpp File Reference

#include "RISCVISelDAGToDAG.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCVISelLowering.h"
#include "RISCVInstrInfo.h"
#include "RISCVSelectionDAGInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Alignment.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "RISCVGenDAGISel.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "riscv-isel"
#define	PASS_NAME   "RISC-V DAG->DAG Pattern Instruction Selection"
#define	GET_DAGISEL_BODY   RISCVDAGToDAGISel
#define	INST_NF_CASE(NAME, NF)
#define	INST_NF_CASE_MASK(NAME, NF)
#define	INST_NF_CASE_FF(NAME, NF)
#define	INST_NF_CASE_FF_MASK(NAME, NF)
#define	INST_ALL_NF_CASE_BASE(MACRO_NAME, NAME)
#define	INST_ALL_NF_CASE(NAME)
#define	INST_ALL_NF_CASE_WITH_FF(NAME)
#define	CASE_VMSLT_OPCODES(lmulenum, suffix)
#define	CASE_VMNAND_VMSET_OPCODES(lmulenum, suffix)
#define	CASE_VMSLT_OPCODES(lmulenum, suffix)
#define	CASE_VMXOR_VMANDN_VMOR_OPCODES(lmulenum, suffix)

Functions
static SDValue	selectImmSeq (SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, RISCVMatInt::InstSeq &Seq)
static SDValue	selectImm (SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, int64_t Imm, const RISCVSubtarget &Subtarget)
static unsigned	getSegInstNF (unsigned Intrinsic)
static bool	selectConstantAddr (SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, const RISCVSubtarget *Subtarget, SDValue Addr, SDValue &Base, SDValue &Offset, bool IsPrefetch=false)
static bool	isWorthFoldingAdd (SDValue Add)
static bool	isRegRegScaleLoadOrStore (SDNode *User, SDValue Add, const RISCVSubtarget &Subtarget)
	Return true if this a load/store that we have a RegRegScale instruction for.
static bool	isWorthFoldingIntoRegRegScale (const RISCVSubtarget &Subtarget, SDValue Add, SDValue Shift=SDValue())
	Is it profitable to fold this Add into RegRegScale load/store.
static bool	vectorPseudoHasAllNBitUsers (SDNode *User, unsigned UserOpNo, unsigned Bits, const TargetInstrInfo *TII)
static SDValue	findVSplat (SDValue N)
static bool	selectVSplatImmHelper (SDValue N, SDValue &SplatVal, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, std::function< bool(int64_t)> ValidateImm, bool Decrement=false)
static bool	usesAllOnesMask (SDValue MaskOp)
static bool	isImplicitDef (SDValue V)

Variables
static cl::opt< bool >	UsePseudoMovImm ("riscv-use-rematerializable-movimm", cl::Hidden, cl::desc("Use a rematerializable pseudoinstruction for 2 instruction " "constant materialization"), cl::init(false))

Macro Definition Documentation

CASE_VMNAND_VMSET_OPCODES

#define CASE_VMNAND_VMSET_OPCODES	(		lmulenum,
			suffix
	)

Value:

  case RISCVVType::lmulenum:                                                   \
    VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix;                            \
    VMSetOpcode = RISCV::PseudoVMSET_M_##suffix;                               \
    break;

CASE_VMSLT_OPCODES [1/2]

#define CASE_VMSLT_OPCODES	(		lmulenum,
			suffix
	)

Value:

  case RISCVVType::lmulenum:                                                   \
    VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix                 \
                             : RISCV::PseudoVMSLT_VX_##suffix;                 \
    VMSGTOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix                 \
                             : RISCV::PseudoVMSGT_VX_##suffix;                 \
    break;

CASE_VMSLT_OPCODES [2/2]

#define CASE_VMSLT_OPCODES	(		lmulenum,
			suffix
	)

Value:

  case RISCVVType::lmulenum:                                                   \
    VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix                 \
                             : RISCV::PseudoVMSLT_VX_##suffix;                 \
    VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix##_MASK      \
                                 : RISCV::PseudoVMSLT_VX_##suffix##_MASK;      \
    VMSGTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix##_MASK      \
                                 : RISCV::PseudoVMSGT_VX_##suffix##_MASK;      \
    break;

CASE_VMXOR_VMANDN_VMOR_OPCODES

#define CASE_VMXOR_VMANDN_VMOR_OPCODES	(		lmulenum,
			suffix
	)

Value:

  case RISCVVType::lmulenum:                                                   \
    VMXOROpcode = RISCV::PseudoVMXOR_MM_##suffix;                              \
    VMANDNOpcode = RISCV::PseudoVMANDN_MM_##suffix;                            \
    VMOROpcode = RISCV::PseudoVMOR_MM_##suffix;                                \
    break;

DEBUG_TYPE

#define DEBUG_TYPE   "riscv-isel"

Definition at line 30 of file RISCVISelDAGToDAG.cpp.

GET_DAGISEL_BODY

#define GET_DAGISEL_BODY   RISCVDAGToDAGISel

Definition at line 39 of file RISCVISelDAGToDAG.cpp.

INST_ALL_NF_CASE

#define INST_ALL_NF_CASE

(

NAME

)

Value:

  INST_ALL_NF_CASE_BASE(INST_NF_CASE, NAME)                                    \
  INST_ALL_NF_CASE_BASE(INST_NF_CASE_MASK, NAME)

INST_ALL_NF_CASE_BASE

#define INST_ALL_NF_CASE_BASE	(		MACRO_NAME,
			NAME
	)

Value:

  MACRO_NAME(NAME, 2)                                                          \
  MACRO_NAME(NAME, 3)                                                          \
  MACRO_NAME(NAME, 4)                                                          \
  MACRO_NAME(NAME, 5)                                                          \
  MACRO_NAME(NAME, 6)                                                          \
  MACRO_NAME(NAME, 7)                                                          \
  MACRO_NAME(NAME, 8)

INST_ALL_NF_CASE_WITH_FF

#define INST_ALL_NF_CASE_WITH_FF

(

NAME

)

Value:

  INST_ALL_NF_CASE(NAME)                                                       \
  INST_ALL_NF_CASE_BASE(INST_NF_CASE_FF, NAME)                                 \
  INST_ALL_NF_CASE_BASE(INST_NF_CASE_FF_MASK, NAME)

INST_NF_CASE

#define INST_NF_CASE	(		NAME,
			NF
	)

Value:

  case Intrinsic::riscv_##NAME##NF:                                            \
    return NF;

INST_NF_CASE_FF

#define INST_NF_CASE_FF	(		NAME,
			NF
	)

Value:

  case Intrinsic::riscv_##NAME##NF##ff:                                        \
    return NF;

INST_NF_CASE_FF_MASK

#define INST_NF_CASE_FF_MASK	(		NAME,
			NF
	)

Value:

  case Intrinsic::riscv_##NAME##NF##ff_mask:                                   \
    return NF;

INST_NF_CASE_MASK

#define INST_NF_CASE_MASK	(		NAME,
			NF
	)

Value:

  case Intrinsic::riscv_##NAME##NF##_mask:                                     \
    return NF;

PASS_NAME

#define PASS_NAME   "RISC-V DAG->DAG Pattern Instruction Selection"

Definition at line 31 of file RISCVISelDAGToDAG.cpp.

Function Documentation

findVSplat()

static SDValue findVSplat ( SDValue  N )

static

Definition at line 4038 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::ISD::INSERT_SUBVECTOR, N, and llvm::Splat.

Referenced by llvm::RISCVDAGToDAGISel::selectVSplat(), llvm::RISCVDAGToDAGISel::selectVSplatImm64Neg(), and selectVSplatImmHelper().

getSegInstNF()

static unsigned getSegInstNF ( unsigned  Intrinsic )

static

Definition at line 1041 of file RISCVISelDAGToDAG.cpp.

References INST_ALL_NF_CASE, INST_ALL_NF_CASE_WITH_FF, and llvm_unreachable.

Referenced by llvm::RISCVDAGToDAGISel::Select().

isImplicitDef()

static bool isImplicitDef ( SDValue  V )

static

Definition at line 4299 of file RISCVISelDAGToDAG.cpp.

References I, and isImplicitDef().

Referenced by isImplicitDef().

isRegRegScaleLoadOrStore()

static bool isRegRegScaleLoadOrStore ( SDNode *  User, SDValue  Add, const RISCVSubtarget &  Subtarget  )

static

Return true if this a load/store that we have a RegRegScale instruction for.

Definition at line 3139 of file RISCVISelDAGToDAG.cpp.

References llvm::Add, llvm::EVT::isScalarInteger(), llvm::ISD::LOAD, and llvm::ISD::STORE.

Referenced by isWorthFoldingIntoRegRegScale().

isWorthFoldingAdd()

static bool isWorthFoldingAdd ( SDValue  Add )

static

Definition at line 2925 of file RISCVISelDAGToDAG.cpp.

References llvm::Add, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, llvm::User::getOperand(), llvm::EVT::isScalarInteger(), llvm::isStrongerThanMonotonic(), llvm::ISD::LOAD, and llvm::ISD::STORE.

Referenced by llvm::RISCVDAGToDAGISel::SelectAddrRegImm().

isWorthFoldingIntoRegRegScale()

static bool isWorthFoldingIntoRegRegScale ( const RISCVSubtarget &  Subtarget, SDValue  Add, SDValue  Shift = SDValue()  )

static

Is it profitable to fold this Add into RegRegScale load/store.

If Shift is non-null, then we have matched a shl+add. We allow reassociating (add (add (shl A C2) B) C1) -> (add (add B C1) (shl A C2)) if there is a single addi and we don't have a SHXADD instruction we could use. FIXME: May still need to check how many and what kind of users the SHL has.

Definition at line 3162 of file RISCVISelDAGToDAG.cpp.

References llvm::Add, llvm::ISD::ADD, assert(), llvm::User::getOperand(), isRegRegScaleLoadOrStore(), llvm::ISD::SHL, and llvm::Value::users().

Referenced by llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale().

selectConstantAddr()

static bool selectConstantAddr ( SelectionDAG *  CurDAG, const SDLoc &  DL, const MVT  VT, const RISCVSubtarget *  Subtarget, SDValue  Addr, SDValue &  Base, SDValue &  Offset, bool  IsPrefetch = false  )

static

Definition at line 2873 of file RISCVISelDAGToDAG.cpp.

References Addr, assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::sampleprof::Base, DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::Hi, llvm::RISCVSubtarget::is64Bit(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::pop_back(), and selectImmSeq().

Referenced by llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), and llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000().

selectImm()

static SDValue selectImm ( SelectionDAG *  CurDAG, const SDLoc &  DL, const MVT  VT, int64_t  Imm, const RISCVSubtarget &  Subtarget  )

static

Definition at line 208 of file RISCVISelDAGToDAG.cpp.

References DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVMatInt::generateTwoRegInstSeq(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::Lo, selectImmSeq(), llvm::SmallVectorBase< Size_T >::size(), and UsePseudoMovImm.

Referenced by llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectInvLogicImm(), llvm::RISCVDAGToDAGISel::selectScalarFPAsInt(), llvm::RISCVDAGToDAGISel::tryBitfieldInsertOpFromOrAndImm(), and llvm::RISCVDAGToDAGISel::tryBitfieldInsertOpFromXor().

selectImmSeq()

static SDValue selectImmSeq ( SelectionDAG *  CurDAG, const SDLoc &  DL, const MVT  VT, RISCVMatInt::InstSeq &  Seq  )

static

Definition at line 179 of file RISCVISelDAGToDAG.cpp.

References DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::RISCVMatInt::Imm, llvm::RISCVMatInt::RegImm, llvm::RISCVMatInt::RegReg, and llvm::RISCVMatInt::RegX0.

Referenced by selectConstantAddr(), and selectImm().

selectVSplatImmHelper()

static bool selectVSplatImmHelper ( SDValue  N, SDValue &  SplatVal, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget, std::function< bool(int64_t)>  ValidateImm, bool  Decrement = false  )

static

Definition at line 4062 of file RISCVISelDAGToDAG.cpp.

References assert(), findVSplat(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), N, and llvm::Splat.

Referenced by llvm::RISCVDAGToDAGISel::selectVSplatSimm5(), llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1(), llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1NoDec(), llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(), and llvm::RISCVDAGToDAGISel::selectVSplatUimm().

usesAllOnesMask()

static bool usesAllOnesMask ( SDValue  MaskOp )

static

Definition at line 4285 of file RISCVISelDAGToDAG.cpp.

References llvm::SDValue::getMachineOpcode(), llvm::SDNode::isMachineOpcode(), and Opc.

vectorPseudoHasAllNBitUsers()

static bool vectorPseudoHasAllNBitUsers ( SDNode *  User, unsigned  UserOpNo, unsigned  Bits, const TargetInstrInfo *  TII  )

static

Definition at line 3792 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::User::getNumOperands(), llvm::User::getOperand(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCV::getVectorLowDemandedScalarBits(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVII::hasVLOp(), TII, and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::RISCVDAGToDAGISel::hasAllNBitUsers().

Variable Documentation

UsePseudoMovImm

cl::opt< bool > UsePseudoMovImm("riscv-use-rematerializable-movimm", cl::Hidden, cl::desc("Use a rematerializable pseudoinstruction for 2 instruction " "constant materialization"), cl::init(false)) ( "riscv-use-rematerializable-movimm"  , cl::Hidden  , cl::desc("Use a rematerializable pseudoinstruction for 2 instruction " "constant materialization")  , cl::init(false)    )

static

Referenced by selectImm().