#include "RISCVISelDAGToDAG.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCVISelLowering.h"
#include "RISCVInstrInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Alignment.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "RISCVGenSearchableTables.inc"

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

namespace	llvm::RISCV

Macros
#define	DEBUG_TYPE "riscv-isel"

#define	PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection"

#define	GET_RISCVVSSEGTable_IMPL

#define	GET_RISCVVLSEGTable_IMPL

#define	GET_RISCVVLXSEGTable_IMPL

#define	GET_RISCVVSXSEGTable_IMPL

#define	GET_RISCVVLETable_IMPL

#define	GET_RISCVVSETable_IMPL

#define	GET_RISCVVLXTable_IMPL

#define	GET_RISCVVSXTable_IMPL

#define	INST_NF_CASE(NAME, NF)

#define	INST_NF_CASE_MASK(NAME, NF)

#define	INST_NF_CASE_FF(NAME, NF)

#define	INST_NF_CASE_FF_MASK(NAME, NF)

#define	INST_ALL_NF_CASE_BASE(MACRO_NAME, NAME)

#define	INST_ALL_NF_CASE(NAME)

#define	INST_ALL_NF_CASE_WITH_FF(NAME)

#define	CASE_VMSLT_OPCODES(lmulenum, suffix)

#define	CASE_VMNAND_VMSET_OPCODES(lmulenum, suffix)

#define	CASE_VMSLT_OPCODES(lmulenum, suffix)

#define	CASE_VMXOR_VMANDN_VMOR_OPCODES(lmulenum, suffix)

Functions
static SDValue	selectImmSeq (SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, RISCVMatInt::InstSeq &Seq)

static SDValue	selectImm (SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, int64_t Imm, const RISCVSubtarget &Subtarget)

static unsigned	getSegInstNF (unsigned Intrinsic)

static bool	selectConstantAddr (SelectionDAG CurDAG, const SDLoc &DL, const MVT VT, const RISCVSubtarget Subtarget, SDValue Addr, SDValue &Base, SDValue &Offset, bool IsPrefetch=false, bool IsRV32Zdinx=false)

static bool	isWorthFoldingAdd (SDValue Add)

static bool	vectorPseudoHasAllNBitUsers (SDNode User, unsigned UserOpNo, unsigned Bits, const TargetInstrInfo TII)

static SDValue	findVSplat (SDValue N)

static bool	selectVSplatImmHelper (SDValue N, SDValue &SplatVal, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, std::function< bool(int64_t)> ValidateImm)

static SDValue	getMaskSetter (SDValue MaskOp, SDValue GlueOp)

static bool	usesAllOnesMask (SDValue MaskOp, SDValue GlueOp)

static bool	usesAllOnesMask (SDNode *N, unsigned MaskOpIdx)

static bool	isImplicitDef (SDValue V)

static bool	hasGPROut (unsigned Opc)

static bool	IsVMerge (SDNode *N)

Variables
static cl::opt< bool >	UsePseudoMovImm ("riscv-use-rematerializable-movimm", cl::Hidden, cl::desc("Use a rematerializable pseudoinstruction for 2 instruction " "constant materialization"), cl::init(false))

Macro Definition Documentation

◆ CASE_VMNAND_VMSET_OPCODES

#define CASE_VMNAND_VMSET_OPCODES	(	lmulenum,
		suffix
	)

Value:

  case RISCVII::VLMUL::lmulenum:                                               \
    VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix;                            \
    VMSetOpcode = RISCV::PseudoVMSET_M_##suffix;                               \
    break;

◆ CASE_VMSLT_OPCODES [1/2]

#define CASE_VMSLT_OPCODES	(	lmulenum,
		suffix
	)

Value:

  case RISCVII::VLMUL::lmulenum:                                               \
    VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix                 \
                             : RISCV::PseudoVMSLT_VX_##suffix;                 \
    VMSGTOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix                 \
                             : RISCV::PseudoVMSGT_VX_##suffix;                 \
    break;

◆ CASE_VMSLT_OPCODES [2/2]

#define CASE_VMSLT_OPCODES	(	lmulenum,
		suffix
	)

Value:

  case RISCVII::VLMUL::lmulenum:                                               \
    VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix                 \
                             : RISCV::PseudoVMSLT_VX_##suffix;                 \
    VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix##_MASK      \
                                 : RISCV::PseudoVMSLT_VX_##suffix##_MASK;      \
    VMSGTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix##_MASK      \
                                 : RISCV::PseudoVMSGT_VX_##suffix##_MASK;      \
    break;

◆ CASE_VMXOR_VMANDN_VMOR_OPCODES

#define CASE_VMXOR_VMANDN_VMOR_OPCODES	(	lmulenum,
		suffix
	)

Value:

  case RISCVII::VLMUL::lmulenum:                                               \
    VMXOROpcode = RISCV::PseudoVMXOR_MM_##suffix;                              \
    VMANDNOpcode = RISCV::PseudoVMANDN_MM_##suffix;                            \
    VMOROpcode = RISCV::PseudoVMOR_MM_##suffix;                                \
    break;

◆ DEBUG_TYPE

#define DEBUG_TYPE "riscv-isel"

Definition at line 28 of file RISCVISelDAGToDAG.cpp.

◆ GET_RISCVVLETable_IMPL

#define GET_RISCVVLETable_IMPL

Definition at line 42 of file RISCVISelDAGToDAG.cpp.

◆ GET_RISCVVLSEGTable_IMPL

#define GET_RISCVVLSEGTable_IMPL

Definition at line 39 of file RISCVISelDAGToDAG.cpp.

◆ GET_RISCVVLXSEGTable_IMPL

#define GET_RISCVVLXSEGTable_IMPL

Definition at line 40 of file RISCVISelDAGToDAG.cpp.

◆ GET_RISCVVLXTable_IMPL

#define GET_RISCVVLXTable_IMPL

Definition at line 44 of file RISCVISelDAGToDAG.cpp.

◆ GET_RISCVVSETable_IMPL

#define GET_RISCVVSETable_IMPL

Definition at line 43 of file RISCVISelDAGToDAG.cpp.

◆ GET_RISCVVSSEGTable_IMPL

#define GET_RISCVVSSEGTable_IMPL

Definition at line 38 of file RISCVISelDAGToDAG.cpp.

◆ GET_RISCVVSXSEGTable_IMPL

#define GET_RISCVVSXSEGTable_IMPL

Definition at line 41 of file RISCVISelDAGToDAG.cpp.

◆ GET_RISCVVSXTable_IMPL

#define GET_RISCVVSXTable_IMPL

Definition at line 45 of file RISCVISelDAGToDAG.cpp.

◆ INST_ALL_NF_CASE

#define INST_ALL_NF_CASE ( NAME )

Value:

INST_ALL_NF_CASE_BASE(INST_NF_CASE, NAME) \

INST_ALL_NF_CASE_BASE(INST_NF_CASE_MASK, NAME)

INST_NF_CASE

#define INST_NF_CASE(NAME, NF)

INST_ALL_NF_CASE_BASE

#define INST_ALL_NF_CASE_BASE(MACRO_NAME, NAME)

INST_NF_CASE_MASK

#define INST_NF_CASE_MASK(NAME, NF)

◆ INST_ALL_NF_CASE_BASE

#define INST_ALL_NF_CASE_BASE	(	MACRO_NAME,
		NAME
	)

Value:

  MACRO_NAME(NAME, 2)                                                          \
  MACRO_NAME(NAME, 3)                                                          \
  MACRO_NAME(NAME, 4)                                                          \
  MACRO_NAME(NAME, 5)                                                          \
  MACRO_NAME(NAME, 6)                                                          \
  MACRO_NAME(NAME, 7)                                                          \
  MACRO_NAME(NAME, 8)

◆ INST_ALL_NF_CASE_WITH_FF

#define INST_ALL_NF_CASE_WITH_FF ( NAME )

Value:

  INST_ALL_NF_CASE(NAME)                                                       \
  INST_ALL_NF_CASE_BASE(INST_NF_CASE_FF, NAME)                                 \
  INST_ALL_NF_CASE_BASE(INST_NF_CASE_FF_MASK, NAME)

◆ INST_NF_CASE

#define INST_NF_CASE	(	NAME,
		NF
	)

Value:

case Intrinsic::riscv_##NAME##NF: \

return NF;

◆ INST_NF_CASE_FF

#define INST_NF_CASE_FF	(	NAME,
		NF
	)

Value:

case Intrinsic::riscv_##NAME##NF##ff: \

return NF;

◆ INST_NF_CASE_FF_MASK

#define INST_NF_CASE_FF_MASK	(	NAME,
		NF
	)

Value:

case Intrinsic::riscv_##NAME##NF##ff_mask: \

return NF;

◆ INST_NF_CASE_MASK

#define INST_NF_CASE_MASK	(	NAME,
		NF
	)

Value:

case Intrinsic::riscv_##NAME##NF##_mask: \

return NF;

◆ PASS_NAME

#define PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection"

Definition at line 29 of file RISCVISelDAGToDAG.cpp.

Function Documentation

◆ findVSplat()

static SDValue findVSplat ( SDValue N )

static

Definition at line 3519 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::ISD::INSERT_SUBVECTOR, N, llvm::Splat, llvm::RISCVISD::VMV_S_X_VL, and llvm::RISCVISD::VMV_V_X_VL.

Referenced by llvm::RISCVDAGToDAGISel::selectVSplat(), and selectVSplatImmHelper().

◆ getMaskSetter()

static SDValue getMaskSetter	(	SDValue	MaskOp,
		SDValue	GlueOp
	)

static

Definition at line 3750 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::CopyToReg, llvm::SDNode::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), getReg(), and llvm::SDNode::isMachineOpcode().

Referenced by usesAllOnesMask().

◆ getSegInstNF()

static unsigned getSegInstNF ( unsigned Intrinsic )

static

Definition at line 799 of file RISCVISelDAGToDAG.cpp.

References INST_ALL_NF_CASE, INST_ALL_NF_CASE_WITH_FF, and llvm_unreachable.

Referenced by llvm::RISCVDAGToDAGISel::Select().

◆ hasGPROut()

static bool hasGPROut ( unsigned Opc )

static

Definition at line 3816 of file RISCVISelDAGToDAG.cpp.

References llvm::RISCV::getRVVMCOpcode().

◆ isImplicitDef()

static bool isImplicitDef ( SDValue V )

static

Definition at line 3804 of file RISCVISelDAGToDAG.cpp.

References I, and isImplicitDef().

Referenced by isImplicitDef().

◆ IsVMerge()

static bool IsVMerge ( SDNode * N )

static

Definition at line 3881 of file RISCVISelDAGToDAG.cpp.

References llvm::RISCV::getRVVMCOpcode(), and N.

◆ isWorthFoldingAdd()

static bool isWorthFoldingAdd ( SDValue Add )

static

Definition at line 2616 of file RISCVISelDAGToDAG.cpp.

References llvm::Add, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, llvm::EVT::isScalarInteger(), llvm::ISD::LOAD, and llvm::ISD::STORE.

Referenced by llvm::RISCVDAGToDAGISel::SelectAddrRegImm().

◆ selectConstantAddr()

static bool selectConstantAddr	(	SelectionDAG *	CurDAG,
		const SDLoc &	DL,
		const MVT	VT,
		const RISCVSubtarget *	Subtarget,
		SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset,
		bool	IsPrefetch = `false`,
		bool	IsRV32Zdinx = `false`
	)

static

◆ selectImm()

static SDValue selectImm	(	SelectionDAG *	CurDAG,
		const SDLoc &	DL,
		const MVT	VT,
		int64_t	Imm,
		const RISCVSubtarget &	Subtarget
	)

static

Definition at line 204 of file RISCVISelDAGToDAG.cpp.

References DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVMatInt::generateTwoRegInstSeq(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::Lo, selectImmSeq(), llvm::SmallVectorBase< Size_T >::size(), and UsePseudoMovImm.

Referenced by llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectInvLogicImm(), and llvm::RISCVDAGToDAGISel::selectScalarFPAsInt().

◆ selectImmSeq()

static SDValue selectImmSeq	(	SelectionDAG *	CurDAG,
		const SDLoc &	DL,
		const MVT	VT,
		RISCVMatInt::InstSeq &	Seq
	)

static

Definition at line 175 of file RISCVISelDAGToDAG.cpp.

References DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::RISCVMatInt::Imm, llvm::RISCVMatInt::RegImm, llvm::RISCVMatInt::RegReg, and llvm::RISCVMatInt::RegX0.

Referenced by selectConstantAddr(), and selectImm().

◆ selectVSplatImmHelper()

static bool selectVSplatImmHelper	(	SDValue	N,
		SDValue &	SplatVal,
		SelectionDAG &	DAG,
		const RISCVSubtarget &	Subtarget,
		std::function< bool(int64_t)>	ValidateImm
	)

static

Definition at line 3543 of file RISCVISelDAGToDAG.cpp.

References assert(), findVSplat(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), N, and llvm::Splat.

Referenced by llvm::RISCVDAGToDAGISel::selectVSplatSimm5(), llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1(), llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(), and llvm::RISCVDAGToDAGISel::selectVSplatUimm().

◆ usesAllOnesMask() [1/2]

static bool usesAllOnesMask	(	SDNode *	N,
		unsigned	MaskOpIdx
	)

static

Definition at line 3799 of file RISCVISelDAGToDAG.cpp.

References N, and usesAllOnesMask().

◆ usesAllOnesMask() [2/2]

static bool usesAllOnesMask	(	SDValue	MaskOp,
		SDValue	GlueOp
	)

static

Definition at line 3778 of file RISCVISelDAGToDAG.cpp.

References llvm::SDValue::getMachineOpcode(), getMaskSetter(), and llvm::SDNode::isMachineOpcode().

Referenced by usesAllOnesMask().

◆ vectorPseudoHasAllNBitUsers()

static bool vectorPseudoHasAllNBitUsers	(	SDNode *	User,
		unsigned	UserOpNo,
		unsigned	Bits,
		const TargetInstrInfo *	TII
	)

static

Definition at line 3268 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::User::getNumOperands(), llvm::User::getOperand(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCV::getVectorLowDemandedScalarBits(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVII::hasVLOp(), TII, and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::RISCVDAGToDAGISel::hasAllNBitUsers().

Variable Documentation

◆ UsePseudoMovImm

cl::opt< bool > UsePseudoMovImm("riscv-use-rematerializable-movimm", cl::Hidden, cl::desc("Use a rematerializable pseudoinstruction for 2 instruction " "constant materialization"), cl::init(false))	(	"riscv-use-rematerializable-movimm"	,
		cl::Hidden	,
		cl::desc("Use a rematerializable pseudoinstruction for 2 instruction " "constant materialization")	,
		cl::init(false)
	)

static

Referenced by selectImm().

Namespaces

Macros

Functions

Variables

Macro Definition Documentation

◆ CASE_VMNAND_VMSET_OPCODES

◆ CASE_VMSLT_OPCODES [1/2]

◆ CASE_VMSLT_OPCODES [2/2]

◆ CASE_VMXOR_VMANDN_VMOR_OPCODES

◆ DEBUG_TYPE

◆ GET_RISCVVLETable_IMPL

◆ GET_RISCVVLSEGTable_IMPL

◆ GET_RISCVVLXSEGTable_IMPL

◆ GET_RISCVVLXTable_IMPL

◆ GET_RISCVVSETable_IMPL

◆ GET_RISCVVSSEGTable_IMPL

◆ GET_RISCVVSXSEGTable_IMPL

◆ GET_RISCVVSXTable_IMPL

◆ INST_ALL_NF_CASE

◆ INST_ALL_NF_CASE_BASE

◆ INST_ALL_NF_CASE_WITH_FF

◆ INST_NF_CASE

◆ INST_NF_CASE_FF

◆ INST_NF_CASE_FF_MASK

◆ INST_NF_CASE_MASK

◆ PASS_NAME

Function Documentation

◆ findVSplat()

◆ getMaskSetter()

◆ getSegInstNF()

◆ hasGPROut()

◆ isImplicitDef()

◆ IsVMerge()

◆ isWorthFoldingAdd()

◆ selectConstantAddr()

◆ selectImm()

◆ selectImmSeq()

◆ selectVSplatImmHelper()

◆ usesAllOnesMask() [1/2]

◆ usesAllOnesMask() [2/2]

◆ vectorPseudoHasAllNBitUsers()

Variable Documentation

◆ UsePseudoMovImm