LLVM 20.0.0git
RISCVPostRAExpandPseudoInsts.cpp
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1//===-- RISCVPostRAExpandPseudoInsts.cpp - Expand pseudo instrs ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands the pseudo instruction pseudolisimm32
10// into target instructions. This pass should be run during the post-regalloc
11// passes, before post RA scheduling.
12//
13//===----------------------------------------------------------------------===//
14
16#include "RISCV.h"
17#include "RISCVInstrInfo.h"
18#include "RISCVTargetMachine.h"
21
22using namespace llvm;
23
24#define RISCV_POST_RA_EXPAND_PSEUDO_NAME \
25 "RISC-V post-regalloc pseudo instruction expansion pass"
26
27namespace {
28
29class RISCVPostRAExpandPseudo : public MachineFunctionPass {
30public:
31 const RISCVInstrInfo *TII;
32 static char ID;
33
34 RISCVPostRAExpandPseudo() : MachineFunctionPass(ID) {}
35
36 bool runOnMachineFunction(MachineFunction &MF) override;
37
38 StringRef getPassName() const override {
40 }
41
42private:
43 bool expandMBB(MachineBasicBlock &MBB);
48};
49
50char RISCVPostRAExpandPseudo::ID = 0;
51
52bool RISCVPostRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
53 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
54 bool Modified = false;
55 for (auto &MBB : MF)
56 Modified |= expandMBB(MBB);
57 return Modified;
58}
59
60bool RISCVPostRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
61 bool Modified = false;
62
64 while (MBBI != E) {
65 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
66 Modified |= expandMI(MBB, MBBI, NMBBI);
67 MBBI = NMBBI;
68 }
69
70 return Modified;
71}
72
73bool RISCVPostRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
76 switch (MBBI->getOpcode()) {
77 case RISCV::PseudoMovImm:
78 return expandMovImm(MBB, MBBI);
79 case RISCV::PseudoMovAddr:
80 return expandMovAddr(MBB, MBBI);
81 default:
82 return false;
83 }
84}
85
86bool RISCVPostRAExpandPseudo::expandMovImm(MachineBasicBlock &MBB,
88 DebugLoc DL = MBBI->getDebugLoc();
89
90 int64_t Val = MBBI->getOperand(1).getImm();
91
92 Register DstReg = MBBI->getOperand(0).getReg();
93 bool DstIsDead = MBBI->getOperand(0).isDead();
94 bool Renamable = MBBI->getOperand(0).isRenamable();
95
96 TII->movImm(MBB, MBBI, DL, DstReg, Val, MachineInstr::NoFlags, Renamable,
97 DstIsDead);
98
100 return true;
101}
102
103bool RISCVPostRAExpandPseudo::expandMovAddr(MachineBasicBlock &MBB,
105 DebugLoc DL = MBBI->getDebugLoc();
106
107 Register DstReg = MBBI->getOperand(0).getReg();
108 bool DstIsDead = MBBI->getOperand(0).isDead();
109 bool Renamable = MBBI->getOperand(0).isRenamable();
110
111 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LUI))
112 .addReg(DstReg, RegState::Define | getRenamableRegState(Renamable))
113 .add(MBBI->getOperand(1));
114 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI))
115 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead) |
116 getRenamableRegState(Renamable))
117 .addReg(DstReg, RegState::Kill | getRenamableRegState(Renamable))
118 .add(MBBI->getOperand(2));
120 return true;
121}
122
123} // end of anonymous namespace
124
125INITIALIZE_PASS(RISCVPostRAExpandPseudo, "riscv-expand-pseudolisimm32",
127namespace llvm {
128
130 return new RISCVPostRAExpandPseudo();
131}
132
133} // end of namespace llvm
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
const HexagonInstrInfo * TII
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
#define RISCV_POST_RA_EXPAND_PSEUDO_NAME
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:310
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
virtual const TargetInstrInfo * getInstrInfo() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ Define
Register definition.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass * createRISCVPostRAExpandPseudoPass()
unsigned getDeadRegState(bool B)
unsigned getRenamableRegState(bool B)