#include "RISCV.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/InitializePasses.h"

Macros
#define	DEBUG_TYPE "riscv-vl-optimizer"
#define	PASS_NAME "RISC-V VL Optimizer"
#define	VSEG_CASES(Prefix, EEW)
#define	VSSEG_CASES(EEW)
#define	VSSSEG_CASES(EEW)
#define	VSUXSEG_CASES(EEW)
#define	VSOXSEG_CASES(EEW)

Functions
static raw_ostream &	operator<< (raw_ostream &OS, const OperandInfo &OI)
static raw_ostream &	operator<< (raw_ostream &OS, const std::optional< OperandInfo > &OI)
static std::pair< unsigned, bool >	getEMULEqualsEEWDivSEWTimesLMUL (unsigned Log2EEW, const MachineInstr &MI)
	Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and SEW are from the TSFlags of MI.
static unsigned	getIntegerExtensionOperandEEW (unsigned Factor, const MachineInstr &MI, const MachineOperand &MO)
	Dest has EEW=SEW.
static std::optional< unsigned >	getOperandLog2EEW (const MachineOperand &MO)
static std::optional< OperandInfo >	getOperandInfo (const MachineOperand &MO)
static bool	isTupleInsertInstr (const MachineInstr &MI)
	Return true if MI is an instruction used for assembling registers for segmented store instructions, namely, RISCVISD::TUPLE_INSERT.
static bool	isVectorOpUsedAsScalarOp (const MachineOperand &MO)
	Return true if MO is a vector operand but is used as a scalar operand.
static std::optional< DemandedVL >	getMinimumVLForVSLIDEDOWN_VX (const MachineOperand &UserOp, const MachineRegisterInfo *MRI)
	Given a vslidedown.vx like:
static bool	isSegmentedStoreInstr (const MachineInstr &MI)
static bool	isPhysical (const MachineOperand &MO)

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "riscv-vl-optimizer"

Definition at line 38 of file RISCVVLOptimizer.cpp.

◆ PASS_NAME

#define PASS_NAME "RISC-V VL Optimizer"

Definition at line 39 of file RISCVVLOptimizer.cpp.

◆ VSEG_CASES

#define VSEG_CASES	(		Prefix,
			EEW )

Value:

  RISCV::Prefix##SEG2E##EEW##_V:                                               \
  case RISCV::Prefix##SEG3E##EEW##_V:                                          \
  case RISCV::Prefix##SEG4E##EEW##_V:                                          \
  case RISCV::Prefix##SEG5E##EEW##_V:                                          \
  case RISCV::Prefix##SEG6E##EEW##_V:                                          \
  case RISCV::Prefix##SEG7E##EEW##_V:                                          \
  case RISCV::Prefix##SEG8E##EEW##_V

Definition at line 221 of file RISCVVLOptimizer.cpp.

◆ VSOXSEG_CASES

#define VSOXSEG_CASES ( EEW )

Value:

VSEG_CASES(VSOX, I##EEW)

I

#define I(x, y, z)

Definition MD5.cpp:57

VSEG_CASES

#define VSEG_CASES(Prefix, EEW)

Definition RISCVVLOptimizer.cpp:221

Definition at line 232 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

◆ VSSEG_CASES

#define VSSEG_CASES ( EEW )

Value:

VSEG_CASES(VS, EEW)

Definition at line 229 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

◆ VSSSEG_CASES

#define VSSSEG_CASES ( EEW )

Value:

VSEG_CASES(VSS, EEW)

Definition at line 230 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

◆ VSUXSEG_CASES

#define VSUXSEG_CASES ( EEW )

Value:

VSEG_CASES(VSUX, I##EEW)

Definition at line 231 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

Function Documentation

◆ getEMULEqualsEEWDivSEWTimesLMUL()

std::pair< unsigned, bool > getEMULEqualsEEWDivSEWTimesLMUL	(	unsigned	Log2EEW,
		const MachineInstr &	MI )

static

Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and SEW are from the TSFlags of MI.

Definition at line 179 of file RISCVVLOptimizer.cpp.

References llvm::RISCVVType::decodeVLMUL(), llvm::RISCVII::getLMul(), llvm::RISCVII::getSEWOpNum(), and MI.

Referenced by getOperandInfo().

◆ getIntegerExtensionOperandEEW()

unsigned getIntegerExtensionOperandEEW	(	unsigned	Factor,
		const MachineInstr &	MI,
		const MachineOperand &	MO )

static

Dest has EEW=SEW.

Source EEW=SEW/Factor (i.e. F2 => EEW/2). SEW comes from TSFlags of MI.

Definition at line 205 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::getOperandNo(), llvm::RISCVII::getSEWOpNum(), llvm::Log2_32(), and MI.

Referenced by getOperandLog2EEW().

◆ getMinimumVLForVSLIDEDOWN_VX()

std::optional< DemandedVL > getMinimumVLForVSLIDEDOWN_VX	(	const MachineOperand &	UserOp,
		const MachineRegisterInfo *	MRI )

static

Given a vslidedown.vx like:

slideamt = ADDI x, -1 v = PseudoVSLIDEDOWN_VX passthru, src, slideamt, avl=1

v will only read the first slideamt + 1 lanes of src, which = x. This is a common case when lowering extractelement.

Note that if x is 0, slideamt will be all ones. In this case src will be completely slid down and none of its lanes will be read (since slideamt is greater than the largest VLMAX of 65536) so we can demand any minimum VL.

Definition at line 1012 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::RISCV::getRVVMCOpcode(), llvm::MachineOperand::isImm(), llvm::Register::isVirtual(), MI, and MRI.

◆ getOperandInfo()

std::optional< OperandInfo > getOperandInfo ( const MachineOperand & MO )

static

Definition at line 852 of file RISCVVLOptimizer.cpp.

References assert(), getEMULEqualsEEWDivSEWTimesLMUL(), getOperandLog2EEW(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), MI, and llvm::RVV.

◆ getOperandLog2EEW()

std::optional< unsigned > getOperandLog2EEW ( const MachineOperand & MO )

static

Dest EEW encoded in the instruction

Definition at line 234 of file RISCVVLOptimizer.cpp.

References assert(), getIntegerExtensionOperandEEW(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVII::isFirstDefTiedToFirstUse(), llvm::RISCVII::isTiedPseudo(), llvm_unreachable, MI, llvm::MCOI::OPERAND_REGISTER, llvm::RVV, VSOXSEG_CASES, VSSEG_CASES, VSSSEG_CASES, and VSUXSEG_CASES.

Referenced by getOperandInfo().

◆ isPhysical()

bool isPhysical ( const MachineOperand & MO )

static

Definition at line 1273 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::getReg(), llvm::Register::isPhysical(), and llvm::MachineOperand::isReg().

Referenced by llvm::PPCInstrInfo::canInsertSelect(), llvm::MachineOperand::isRenamable(), llvm::MachineOperand::print(), and llvm::MachineOperand::setIsRenamable().

◆ isSegmentedStoreInstr()

bool isSegmentedStoreInstr ( const MachineInstr & MI )

static

Definition at line 1116 of file RISCVVLOptimizer.cpp.

References llvm::RISCV::getRVVMCOpcode(), MI, VSOXSEG_CASES, VSSEG_CASES, VSSSEG_CASES, and VSUXSEG_CASES.

◆ isTupleInsertInstr()

bool isTupleInsertInstr ( const MachineInstr & MI )

static

Return true if MI is an instruction used for assembling registers for segmented store instructions, namely, RISCVISD::TUPLE_INSERT.

Currently it's lowered to INSERT_SUBREG.

Definition at line 1095 of file RISCVVLOptimizer.cpp.

References assert(), llvm::RISCVVType::decodeVLMUL(), llvm::RISCVRI::getLMul(), llvm::RISCVRI::getNF(), llvm::RISCVRI::isVRegClass(), MI, MRI, llvm::RISCV::RVVBitsPerBlock, TRI, and llvm::TargetRegisterClass::TSFlags.

◆ isVectorOpUsedAsScalarOp()

bool isVectorOpUsedAsScalarOp ( const MachineOperand & MO )

static

Return true if MO is a vector operand but is used as a scalar operand.

Definition at line 920 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), MI, and llvm::RVV.

◆ operator<<() [1/2]

raw_ostream & operator<<	(	raw_ostream &	OS,
		const OperandInfo &	OI )

static

Definition at line 161 of file RISCVVLOptimizer.cpp.

◆ operator<<() [2/2]

raw_ostream & operator<<	(	raw_ostream &	OS,
		const std::optional< OperandInfo > &	OI )

static

Definition at line 167 of file RISCVVLOptimizer.cpp.

Macros

Functions

Macro Definition Documentation

◆ DEBUG_TYPE

◆ PASS_NAME

◆ VSEG_CASES

◆ VSOXSEG_CASES

◆ VSSEG_CASES

◆ VSSSEG_CASES

◆ VSUXSEG_CASES

Function Documentation

◆ getEMULEqualsEEWDivSEWTimesLMUL()

◆ getIntegerExtensionOperandEEW()

◆ getMinimumVLForVSLIDEDOWN_VX()

◆ getOperandInfo()

◆ getOperandLog2EEW()

◆ isPhysical()

◆ isSegmentedStoreInstr()

◆ isTupleInsertInstr()

◆ isVectorOpUsedAsScalarOp()

◆ operator<<() [1/2]

◆ operator<<() [2/2]