#include "RISCV.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/InitializePasses.h"

Macros
#define	DEBUG_TYPE "riscv-vl-optimizer"
#define	PASS_NAME "RISC-V VL Optimizer"
#define	VSEG_CASES(Prefix, EEW)
#define	VSSEG_CASES(EEW)
#define	VSSSEG_CASES(EEW)
#define	VSUXSEG_CASES(EEW)
#define	VSOXSEG_CASES(EEW)

Functions
	INITIALIZE_PASS_BEGIN (RISCVVLOptimizerLegacy, DEBUG_TYPE, PASS_NAME, false, false) FunctionPass *llvm
static raw_ostream &	operator<< (raw_ostream &OS, const OperandInfo &OI)
static raw_ostream &	operator<< (raw_ostream &OS, const std::optional< OperandInfo > &OI)
static std::pair< unsigned, bool >	getEMULEqualsEEWDivSEWTimesLMUL (unsigned Log2EEW, const MachineInstr &MI)
	Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and SEW are from the TSFlags of MI.
static DemandedVL	doubleVL (DemandedVL MinimumVL)
static std::pair< unsigned, bool >	doubleEMUL (std::pair< unsigned, bool > EMUL)
static unsigned	getIntegerExtensionOperandEEW (unsigned Factor, const MachineInstr &MI, unsigned OpIdx)
	Dest has EEW=SEW.
static std::optional< unsigned >	getOperandLog2EEW (const MachineInstr &MI, unsigned OpIdx)
static std::optional< OperandInfo >	getOperandInfo (const MachineInstr &MI, unsigned OpIdx)
static bool	isTupleInsertInstr (const MachineInstr &MI)
	Return true if MI is an instruction used for assembling registers for segmented store instructions, namely, RISCVISD::TUPLE_INSERT.
static bool	isVectorOpUsedAsScalarOp (const MachineInstr &MI, unsigned OpIdx)
	Return true if operand `OpIdx` of `MI` is a vector operand but is used as a scalar operand.
static std::optional< DemandedVL >	getMinimumVLForVSLIDEDOWN_VX (const MachineInstr &MI, unsigned OpIdx, const MachineRegisterInfo *MRI)
	Given a vslidedown.vx like:
static bool	isSegmentedStoreInstr (const MachineInstr &MI)
static bool	isPhysical (const MachineOperand &MO)

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "riscv-vl-optimizer"

Definition at line 40 of file RISCVVLOptimizer.cpp.

◆ PASS_NAME

#define PASS_NAME "RISC-V VL Optimizer"

Definition at line 41 of file RISCVVLOptimizer.cpp.

◆ VSEG_CASES

#define VSEG_CASES	(		Prefix,
			EEW )

Value:

  RISCV::Prefix##SEG2E##EEW##_V:                                               \
  case RISCV::Prefix##SEG3E##EEW##_V:                                          \
  case RISCV::Prefix##SEG4E##EEW##_V:                                          \
  case RISCV::Prefix##SEG5E##EEW##_V:                                          \
  case RISCV::Prefix##SEG6E##EEW##_V:                                          \
  case RISCV::Prefix##SEG7E##EEW##_V:                                          \
  case RISCV::Prefix##SEG8E##EEW##_V

Definition at line 250 of file RISCVVLOptimizer.cpp.

◆ VSOXSEG_CASES

#define VSOXSEG_CASES ( EEW )

Value:

VSEG_CASES(VSOX, I##EEW)

I

#define I(x, y, z)

Definition MD5.cpp:57

VSEG_CASES

#define VSEG_CASES(Prefix, EEW)

Definition RISCVVLOptimizer.cpp:250

Definition at line 261 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

◆ VSSEG_CASES

#define VSSEG_CASES ( EEW )

Value:

VSEG_CASES(VS, EEW)

Definition at line 258 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

◆ VSSSEG_CASES

#define VSSSEG_CASES ( EEW )

Value:

VSEG_CASES(VSS, EEW)

Definition at line 259 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

◆ VSUXSEG_CASES

#define VSUXSEG_CASES ( EEW )

Value:

VSEG_CASES(VSUX, I##EEW)

Definition at line 260 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

Function Documentation

◆ doubleEMUL()

std::pair< unsigned, bool > doubleEMUL ( std::pair< unsigned, bool > EMUL )

static

Definition at line 225 of file RISCVVLOptimizer.cpp.

Referenced by getOperandInfo().

◆ doubleVL()

DemandedVL doubleVL ( DemandedVL MinimumVL )

static

Definition at line 215 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), and llvm::isUInt().

◆ getEMULEqualsEEWDivSEWTimesLMUL()

std::pair< unsigned, bool > getEMULEqualsEEWDivSEWTimesLMUL	(	unsigned	Log2EEW,
		const MachineInstr &	MI )

static

Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and SEW are from the TSFlags of MI.

Definition at line 191 of file RISCVVLOptimizer.cpp.

References llvm::RISCVVType::decodeVLMUL(), llvm::RISCVII::getLMul(), llvm::RISCVII::getSEWOpNum(), and MI.

Referenced by getOperandInfo().

◆ getIntegerExtensionOperandEEW()

unsigned getIntegerExtensionOperandEEW	(	unsigned	Factor,
		const MachineInstr &	MI,
		unsigned	OpIdx )

static

Dest has EEW=SEW.

Source EEW=SEW/Factor (i.e. F2 => EEW/2). SEW comes from TSFlags of MI.

Definition at line 234 of file RISCVVLOptimizer.cpp.

References llvm::RISCVII::getSEWOpNum(), llvm::Log2_32(), and MI.

Referenced by getOperandLog2EEW().

◆ getMinimumVLForVSLIDEDOWN_VX()

std::optional< DemandedVL > getMinimumVLForVSLIDEDOWN_VX	(	const MachineInstr &	MI,
		unsigned	OpIdx,
		const MachineRegisterInfo *	MRI )

static

Given a vslidedown.vx like:

slideamt = ADDI x, -1 v = PseudoVSLIDEDOWN_VX passthru, src, slideamt, avl=1

v will only read the first slideamt + 1 lanes of src, which = x. This is a common case when lowering extractelement.

Note that if x is 0, slideamt will be all ones. In this case src will be completely slid down and none of its lanes will be read (since slideamt is greater than the largest VLMAX of 65536) so we can demand any minimum VL.

Definition at line 1077 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::RISCV::getRVVMCOpcode(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineOperand::isImm(), llvm::Register::isVirtual(), and MI.

◆ getOperandInfo()

std::optional< OperandInfo > getOperandInfo	(	const MachineInstr &	MI,
		unsigned	OpIdx )

static

Definition at line 898 of file RISCVVLOptimizer.cpp.

References assert(), doubleEMUL(), getEMULEqualsEEWDivSEWTimesLMUL(), getOperandLog2EEW(), MI, and llvm::RVV.

◆ getOperandLog2EEW()

std::optional< unsigned > getOperandLog2EEW	(	const MachineInstr &	MI,
		unsigned	OpIdx )

static

Dest EEW encoded in the instruction

Definition at line 263 of file RISCVVLOptimizer.cpp.

References assert(), getIntegerExtensionOperandEEW(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVII::isFirstDefTiedToFirstUse(), llvm::RISCVII::isTiedPseudo(), llvm_unreachable, MI, llvm::MCOI::OPERAND_REGISTER, llvm::RVV, VSOXSEG_CASES, VSSEG_CASES, VSSSEG_CASES, and VSUXSEG_CASES.

Referenced by getOperandInfo().

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	RISCVVLOptimizerLegacy	,
		DEBUG_TYPE	,
		PASS_NAME	,
		false	,
		false	)

Definition at line 163 of file RISCVVLOptimizer.cpp.

References llvm::createRISCVVLOptimizerLegacyPass(), DEBUG_TYPE, INITIALIZE_PASS_DEPENDENCY, INITIALIZE_PASS_END, and PASS_NAME.

◆ isPhysical()

bool isPhysical ( const MachineOperand & MO )

static

Definition at line 1356 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::getReg(), llvm::Register::isPhysical(), and llvm::MachineOperand::isReg().

Referenced by llvm::PPCInstrInfo::canInsertSelect(), llvm::MachineOperand::isRenamable(), llvm::MachineOperand::print(), and llvm::MachineOperand::setIsRenamable().

◆ isSegmentedStoreInstr()

bool isSegmentedStoreInstr ( const MachineInstr & MI )

static

Definition at line 1187 of file RISCVVLOptimizer.cpp.

References llvm::RISCV::getRVVMCOpcode(), MI, VSOXSEG_CASES, VSSEG_CASES, VSSSEG_CASES, and VSUXSEG_CASES.

◆ isTupleInsertInstr()

bool isTupleInsertInstr ( const MachineInstr & MI )

static

Return true if MI is an instruction used for assembling registers for segmented store instructions, namely, RISCVISD::TUPLE_INSERT.

Currently it's lowered to INSERT_SUBREG.

Definition at line 1166 of file RISCVVLOptimizer.cpp.

References assert(), llvm::RISCVVType::decodeVLMUL(), llvm::RISCVRI::getLMul(), llvm::RISCVRI::getNF(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::RISCVRI::isVRegClass(), MI, llvm::RISCV::RVVBitsPerBlock, TRI, and llvm::MCRegisterClass::TSFlags.

◆ isVectorOpUsedAsScalarOp()

bool isVectorOpUsedAsScalarOp	(	const MachineInstr &	MI,
		unsigned	OpIdx )

static

Return true if operand OpIdx of MI is a vector operand but is used as a scalar operand.

Definition at line 986 of file RISCVVLOptimizer.cpp.

References MI, and llvm::RVV.

◆ operator<<() [1/2]

raw_ostream & operator<<	(	raw_ostream &	OS,
		const OperandInfo &	OI )

static

Definition at line 173 of file RISCVVLOptimizer.cpp.

◆ operator<<() [2/2]

raw_ostream & operator<<	(	raw_ostream &	OS,
		const std::optional< OperandInfo > &	OI )

static

Definition at line 179 of file RISCVVLOptimizer.cpp.

Macros

Functions

Macro Definition Documentation

◆ DEBUG_TYPE

◆ PASS_NAME

◆ VSEG_CASES

◆ VSOXSEG_CASES

◆ VSSEG_CASES

◆ VSSSEG_CASES

◆ VSUXSEG_CASES

Function Documentation

◆ doubleEMUL()

◆ doubleVL()

◆ getEMULEqualsEEWDivSEWTimesLMUL()

◆ getIntegerExtensionOperandEEW()

◆ getMinimumVLForVSLIDEDOWN_VX()

◆ getOperandInfo()

◆ getOperandLog2EEW()

◆ INITIALIZE_PASS_BEGIN()

◆ isPhysical()

◆ isSegmentedStoreInstr()

◆ isTupleInsertInstr()

◆ isVectorOpUsedAsScalarOp()

◆ operator<<() [1/2]

◆ operator<<() [2/2]