LLVM 20.0.0git
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#include "X86.h"
#include "X86CallingConv.h"
#include "X86InstrBuilder.h"
#include "X86InstrInfo.h"
#include "X86MachineFunctionInfo.h"
#include "X86RegisterInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/GetElementPtrTypeIterator.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/IntrinsicsX86.h"
#include "llvm/IR/Operator.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetOptions.h"
#include "X86GenFastISel.inc"
Go to the source code of this file.
Namespaces | |
namespace | llvm |
This is an optimization pass for GlobalISel generic memory operations. | |
Macros | |
#define | GET_EGPR_IF_ENABLED(OPC) Subtarget->hasEGPR() ? OPC##_EVEX : OPC |
Functions | |
static std::pair< unsigned, bool > | getX86SSEConditionCode (CmpInst::Predicate Predicate) |
static unsigned | X86ChooseCmpOpcode (EVT VT, const X86Subtarget *Subtarget) |
static unsigned | X86ChooseCmpImmediateOpcode (EVT VT, const ConstantInt *RHSC) |
If we have a comparison with RHS as the RHS of the comparison, return an opcode that works for the compare (e.g. | |
static unsigned | computeBytesPoppedByCalleeForSRet (const X86Subtarget *Subtarget, CallingConv::ID CC, const CallBase *CB) |
#define GET_EGPR_IF_ENABLED | ( | OPC | ) | Subtarget->hasEGPR() ? OPC##_EVEX : OPC |
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Definition at line 3186 of file X86FastISel.cpp.
References llvm::CallBase::arg_empty(), CC, llvm::CallingConv::Fast, llvm::X86Subtarget::getTargetTriple(), llvm::CallingConv::GHC, llvm::CallingConv::HiPE, llvm::Triple::isOSMSVCRT(), llvm::X86Subtarget::isTargetMCU(), llvm::CallBase::paramHasAttr(), llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.
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Definition at line 174 of file X86FastISel.cpp.
References CC, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, and llvm_unreachable.
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If we have a comparison with RHS as the RHS of the comparison, return an opcode that works for the compare (e.g.
CMP32ri) otherwise return 0.
Definition at line 1384 of file X86FastISel.cpp.
References llvm::ConstantInt::getSExtValue(), llvm::EVT::getSimpleVT(), and llvm::MVT::SimpleTy.
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Definition at line 1357 of file X86FastISel.cpp.
References llvm::EVT::getSimpleVT(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), and llvm::MVT::SimpleTy.