#include "Target/AMDGPU/SIMachineScheduler.h"

Inheritance diagram for llvm::SIScheduleDAGMI:

[legend]

Public Member Functions
	SIScheduleDAGMI (MachineSchedContext *C)

	~SIScheduleDAGMI () override

void	schedule () override
	Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.

void	initRPTracker (RegPressureTracker &RPTracker)

MachineBasicBlock *	getBB ()

MachineBasicBlock::iterator	getCurrentTop ()

MachineBasicBlock::iterator	getCurrentBottom ()

LiveIntervals *	getLIS ()

MachineRegisterInfo *	getMRI ()

const TargetRegisterInfo *	getTRI ()

ScheduleDAGTopologicalSort *	GetTopo ()

SUnit &	getEntrySU ()

SUnit &	getExitSU ()

void	restoreSULinksLeft ()

template<typename _Iterator >
void	fillVgprSgprCost (_Iterator First, _Iterator End, unsigned &VgprUsage, unsigned &SgprUsage)

std::set< unsigned >	getInRegs ()

std::set< unsigned >	getOutRegs ()

Public Member Functions inherited from llvm::ScheduleDAGMILive
	ScheduleDAGMILive (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)

	~ScheduleDAGMILive () override

bool	hasVRegLiveness () const override
	Return true if this DAG supports VReg liveness and RegPressure.

bool	isTrackingPressure () const
	Return true if register pressure tracking is enabled.

const IntervalPressure &	getTopPressure () const
	Get current register pressure for the top scheduled instructions.

const RegPressureTracker &	getTopRPTracker () const

const IntervalPressure &	getBotPressure () const
	Get current register pressure for the bottom scheduled instructions.

const RegPressureTracker &	getBotRPTracker () const

const IntervalPressure &	getRegPressure () const
	Get register pressure for the entire scheduling region before scheduling.

const std::vector< PressureChange > &	getRegionCriticalPSets () const

PressureDiff &	getPressureDiff (const SUnit *SU)

const PressureDiff &	getPressureDiff (const SUnit *SU) const

void	computeDFSResult ()
	Compute a DFSResult after DAG building is complete, and before any queue comparisons.

const SchedDFSResult *	getDFSResult () const
	Return a non-null DFS result if the scheduling strategy initialized it.

BitVector &	getScheduledTrees ()

void	enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override
	Implement the ScheduleDAGInstrs interface for handling the next scheduling region.

void	schedule () override
	Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.

unsigned	computeCyclicCriticalPath ()
	Compute the cyclic critical path through the DAG.

void	dump () const override

Public Member Functions inherited from llvm::ScheduleDAGMI
	ScheduleDAGMI (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags)

	~ScheduleDAGMI () override

bool	doMBBSchedRegionsTopDown () const override
	If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB.

LiveIntervals *	getLIS () const

virtual bool	hasVRegLiveness () const
	Return true if this DAG supports VReg liveness and RegPressure.

void	addMutation (std::unique_ptr< ScheduleDAGMutation > Mutation)
	Add a postprocessing step to the DAG builder.

MachineBasicBlock::iterator	top () const

MachineBasicBlock::iterator	bottom () const

void	enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override
	Implement the ScheduleDAGInstrs interface for handling the next scheduling region.

void	schedule () override
	Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.

void	startBlock (MachineBasicBlock *bb) override
	Prepares to perform scheduling in the given block.

void	finishBlock () override
	Cleans up after scheduling in the given block.

void	moveInstruction (MachineInstr *MI, MachineBasicBlock::iterator InsertPos)
	Change the position of an instruction within the basic block and update live ranges and region boundary iterators.

const SUnit *	getNextClusterPred () const

const SUnit *	getNextClusterSucc () const

void	viewGraph (const Twine &Name, const Twine &Title) override
	viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'.

void	viewGraph () override
	Out-of-line implementation with no arguments is handy for gdb.

Public Member Functions inherited from llvm::ScheduleDAGInstrs
void	setDumpDirection (DumpDirection D)

	ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)

	~ScheduleDAGInstrs () override=default

const TargetSchedModel *	getSchedModel () const
	Gets the machine model for instruction scheduling.

const MCSchedClassDesc *	getSchedClass (SUnit *SU) const
	Resolves and cache a resolved scheduling class for an SUnit.

bool	IsReachable (SUnit SU, SUnit TargetSU)
	IsReachable - Checks if SU is reachable from TargetSU.

MachineBasicBlock::iterator	begin () const
	Returns an iterator to the top of the current scheduling region.

MachineBasicBlock::iterator	end () const
	Returns an iterator to the bottom of the current scheduling region.

SUnit *	newSUnit (MachineInstr *MI)
	Creates a new SUnit and return a ptr to it.

SUnit *	getSUnit (MachineInstr *MI) const
	Returns an existing SUnit for this MI, or nullptr.

virtual bool	doMBBSchedRegionsTopDown () const
	If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB.

virtual void	startBlock (MachineBasicBlock *BB)
	Prepares to perform scheduling in the given block.

virtual void	finishBlock ()
	Cleans up after scheduling in the given block.

virtual void	enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
	Initialize the DAG and common scheduler state for a new scheduling region.

virtual void	exitRegion ()
	Called when the scheduler has finished scheduling the current region.

void	buildSchedGraph (AAResults AA, RegPressureTracker RPTracker=nullptr, PressureDiffs PDiffs=nullptr, LiveIntervals LIS=nullptr, bool TrackLaneMasks=false)
	Builds SUnits for the current region.

void	addSchedBarrierDeps ()
	Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier.

virtual void	schedule ()=0
	Orders nodes according to selected style.

virtual void	finalizeSchedule ()
	Allow targets to perform final scheduling actions at the level of the whole MachineFunction.

void	dumpNode (const SUnit &SU) const override

void	dump () const override

std::string	getGraphNodeLabel (const SUnit *SU) const override
	Returns a label for a DAG node that points to an instruction.

std::string	getDAGName () const override
	Returns a label for the region of code covered by the DAG.

void	fixupKills (MachineBasicBlock &MBB)
	Fixes register kill flags that scheduling has made invalid.

bool	canAddEdge (SUnit SuccSU, SUnit PredSU)
	True if an edge can be added from PredSU to SuccSU without creating a cycle.

bool	addEdge (SUnit *SuccSU, const SDep &PredDep)
	Add a DAG edge to the given SU with the given predecessor dependence data.

Public Member Functions inherited from llvm::ScheduleDAG
	ScheduleDAG (const ScheduleDAG &)=delete

ScheduleDAG &	operator= (const ScheduleDAG &)=delete

	ScheduleDAG (MachineFunction &mf)

virtual	~ScheduleDAG ()

void	clearDAG ()
	Clears the DAG state (between regions).

const MCInstrDesc *	getInstrDesc (const SUnit *SU) const
	Returns the MCInstrDesc of this SUnit.

virtual void	viewGraph (const Twine &Name, const Twine &Title)
	Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'.

virtual void	viewGraph ()
	Out-of-line implementation with no arguments is handy for gdb.

virtual void	dumpNode (const SUnit &SU) const =0

virtual void	dump () const =0

void	dumpNodeName (const SUnit &SU) const

virtual std::string	getGraphNodeLabel (const SUnit *SU) const =0
	Returns a label for an SUnit node in a visualization of the ScheduleDAG.

virtual std::string	getDAGName () const =0
	Returns a label for the region of code covered by the DAG.

virtual void	addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const
	Adds custom features for a visualization of the ScheduleDAG.

unsigned	VerifyScheduledDAG (bool isBottomUp)
	Verifies that all SUnits were scheduled and that their state is consistent.

Public Attributes
std::vector< unsigned >	IsLowLatencySU

std::vector< unsigned >	LowLatencyOffset

std::vector< unsigned >	IsHighLatencySU

std::vector< int >	TopDownIndex2SU

std::vector< int >	BottomUpIndex2SU

Public Attributes inherited from llvm::ScheduleDAG
const TargetMachine &	TM
	Target processor.

const TargetInstrInfo *	TII
	Target instruction information.

const TargetRegisterInfo *	TRI
	Target processor register info.

MachineFunction &	MF
	Machine function.

MachineRegisterInfo &	MRI
	Virtual/real register map.

std::vector< SUnit >	SUnits
	The scheduling units.

SUnit	EntrySU
	Special node for the region entry.

SUnit	ExitSU
	Special node for the region exit.

bool	StressSched

Additional Inherited Members
Public Types inherited from llvm::ScheduleDAGInstrs
enum	DumpDirection { TopDown , BottomUp , Bidirectional , NotSet }
	The direction that should be used to dump the scheduled Sequence. More...

using	SUList = std::list< SUnit * >
	A list of SUnits, used in Value2SUsMap, during DAG construction.

Protected Types inherited from llvm::ScheduleDAGInstrs
using	DbgValueVector = std::vector< std::pair< MachineInstr , MachineInstr > >

Protected Member Functions inherited from llvm::ScheduleDAGMILive
void	buildDAGWithRegPressure ()
	Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking enabled.

void	initQueues (ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots)
	Release ExitSU predecessors and setup scheduler queues.

void	scheduleMI (SUnit *SU, bool IsTopNode)
	Move an instruction and update register pressure.

void	initRegPressure ()

void	updatePressureDiffs (ArrayRef< RegisterMaskPair > LiveUses)
	Update the PressureDiff array for liveness after scheduling this instruction.

void	updateScheduledPressure (const SUnit *SU, const std::vector< unsigned > &NewMaxPressure)

void	collectVRegUses (SUnit &SU)

Protected Member Functions inherited from llvm::ScheduleDAGMI
void	postProcessDAG ()
	Apply each ScheduleDAGMutation step in order.

void	initQueues (ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots)
	Release ExitSU predecessors and setup scheduler queues.

void	updateQueues (SUnit *SU, bool IsTopNode)
	Update scheduler DAG and queues after scheduling an instruction.

void	placeDebugValues ()
	Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.

void	dumpSchedule () const
	dump the scheduled Sequence.

void	dumpScheduleTraceTopDown () const
	Print execution trace of the schedule top-down or bottom-up.

void	dumpScheduleTraceBottomUp () const

bool	checkSchedLimit ()

void	findRootsAndBiasEdges (SmallVectorImpl< SUnit * > &TopRoots, SmallVectorImpl< SUnit * > &BotRoots)

void	releaseSucc (SUnit SU, SDep SuccEdge)
	ReleaseSucc - Decrement the NumPredsLeft count of a successor.

void	releaseSuccessors (SUnit *SU)
	releaseSuccessors - Call releaseSucc on each of SU's successors.

void	releasePred (SUnit SU, SDep PredEdge)
	ReleasePred - Decrement the NumSuccsLeft count of a predecessor.

void	releasePredecessors (SUnit *SU)
	releasePredecessors - Call releasePred on each of SU's predecessors.

Protected Member Functions inherited from llvm::ScheduleDAGInstrs
void	reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
	Reduces maps in FIFO order, by N SUs.

void	addChainDependency (SUnit SUa, SUnit SUb, unsigned Latency=0)
	Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the dependency.

void	addChainDependencies (SUnit *SU, SUList &SUs, unsigned Latency)
	Adds dependencies as needed from all SUs in list to SU.

void	addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap)
	Adds dependencies as needed from all SUs in map, to SU.

void	addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V)
	Adds dependencies as needed to SU, from all SUs mapped to V.

void	addBarrierChain (Value2SUsMap &map)
	Adds barrier chain edges from all SUs in map, and then clear the map.

void	insertBarrierChain (Value2SUsMap &map)
	Inserts a barrier chain in a huge region, far below current SU.

void	initSUnits ()
	Creates an SUnit for each real instruction, numbered in top-down topological order.

void	addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
	MO is an operand of SU's instruction that defines a physical register.

void	addPhysRegDeps (SUnit *SU, unsigned OperIdx)
	Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx.

void	addVRegDefDeps (SUnit *SU, unsigned OperIdx)
	Adds register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx.

void	addVRegUseDeps (SUnit *SU, unsigned OperIdx)
	Adds a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit.

LaneBitmask	getLaneMaskForMO (const MachineOperand &MO) const
	Returns a mask for which lanes get read/written by the given (register) machine operand.

bool	deadDefHasNoUse (const MachineOperand &MO)
	Returns true if the def register in `MO` has no uses.

Protected Member Functions inherited from llvm::ScheduleDAG
void	dumpNodeAll (const SUnit &SU) const

Protected Attributes inherited from llvm::ScheduleDAGMILive
RegisterClassInfo *	RegClassInfo

SchedDFSResult *	DFSResult = nullptr
	Information about DAG subtrees.

BitVector	ScheduledTrees

MachineBasicBlock::iterator	LiveRegionEnd

VReg2SUnitMultiMap	VRegUses
	Maps vregs to the SUnits of their uses in the current scheduling region.

PressureDiffs	SUPressureDiffs

bool	ShouldTrackPressure = false
	Register pressure in this region computed by initRegPressure.

bool	ShouldTrackLaneMasks = false

IntervalPressure	RegPressure

RegPressureTracker	RPTracker

std::vector< PressureChange >	RegionCriticalPSets
	List of pressure sets that exceed the target's pressure limit before scheduling, listed in increasing set ID order.

IntervalPressure	TopPressure
	The top of the unscheduled zone.

RegPressureTracker	TopRPTracker

IntervalPressure	BotPressure
	The bottom of the unscheduled zone.

RegPressureTracker	BotRPTracker

Protected Attributes inherited from llvm::ScheduleDAGMI
AAResults *	AA

LiveIntervals *	LIS

std::unique_ptr< MachineSchedStrategy >	SchedImpl

std::vector< std::unique_ptr< ScheduleDAGMutation > >	Mutations
	Ordered list of DAG postprocessing steps.

MachineBasicBlock::iterator	CurrentTop
	The top of the unscheduled zone.

MachineBasicBlock::iterator	CurrentBottom
	The bottom of the unscheduled zone.

const SUnit *	NextClusterPred = nullptr
	Record the next node in a scheduled cluster.

const SUnit *	NextClusterSucc = nullptr

Protected Attributes inherited from llvm::ScheduleDAGInstrs
const MachineLoopInfo *	MLI = nullptr

const MachineFrameInfo &	MFI

TargetSchedModel	SchedModel
	TargetSchedModel provides an interface to the machine model.

bool	RemoveKillFlags
	True if the DAG builder should remove kill flags (in preparation for rescheduling).

bool	CanHandleTerminators = false
	The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering.

bool	TrackLaneMasks = false
	Whether lane masks should get tracked.

MachineBasicBlock *	BB = nullptr
	The block in which to insert instructions.

MachineBasicBlock::iterator	RegionBegin
	The beginning of the range to be scheduled.

MachineBasicBlock::iterator	RegionEnd
	The end of the range to be scheduled.

unsigned	NumRegionInstrs = 0
	Instructions in this region (distance(RegionBegin, RegionEnd)).

DenseMap< MachineInstr , SUnit >	MISUnitMap
	After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit.

RegUnit2SUnitsMap	Defs
	Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions.

RegUnit2SUnitsMap	Uses

VReg2SUnitMultiMap	CurrentVRegDefs
	Tracks the last instruction(s) in this region defining each virtual register.

VReg2SUnitOperIdxMultiMap	CurrentVRegUses
	Tracks the last instructions in this region using each virtual register.

AAResults *	AAForDep = nullptr

SUnit *	BarrierChain = nullptr
	Remember a generic side-effecting instruction as we proceed.

DumpDirection	DumpDir = NotSet

UndefValue *	UnknownValue
	For an unanalyzable memory access, this Value is used in maps.

ScheduleDAGTopologicalSort	Topo
	Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.

DbgValueVector	DbgValues
	Remember instruction that precedes DBG_VALUE.

MachineInstr *	FirstDbgValue = nullptr

LiveRegUnits	LiveRegs
	Set of live physical registers for updating kill flags.

Detailed Description

Definition at line 425 of file SIMachineScheduler.h.

Constructor & Destructor Documentation

◆ SIScheduleDAGMI()

SIScheduleDAGMI::SIScheduleDAGMI ( MachineSchedContext * C )

Definition at line 1746 of file SIMachineScheduler.cpp.

References llvm::ScheduleDAG::TII, and llvm::ScheduleDAG::TRI.

◆ ~SIScheduleDAGMI()

SIScheduleDAGMI::~SIScheduleDAGMI ( )

overridedefault

Member Function Documentation

◆ fillVgprSgprCost()

template<typename _Iterator >

void SIScheduleDAGMI::fillVgprSgprCost	(	_Iterator	First,
		_Iterator	End,
		unsigned &	VgprUsage,
		unsigned &	SgprUsage
	)

Definition at line 1849 of file SIMachineScheduler.cpp.

References End, llvm::First, llvm::MachineRegisterInfo::getPressureSets(), llvm::PSetIterator::getWeight(), llvm::PSetIterator::isValid(), llvm::ScheduleDAG::MRI, and Reg.

◆ getBB()

MachineBasicBlock * llvm::SIScheduleDAGMI::getBB ( )

inline

Definition at line 448 of file SIMachineScheduler.h.

References llvm::ScheduleDAGInstrs::BB.

◆ getCurrentBottom()

MachineBasicBlock::iterator llvm::SIScheduleDAGMI::getCurrentBottom ( )

inline

Definition at line 450 of file SIMachineScheduler.h.

References llvm::ScheduleDAGMI::CurrentBottom.

◆ getCurrentTop()

MachineBasicBlock::iterator llvm::SIScheduleDAGMI::getCurrentTop ( )

inline

Definition at line 449 of file SIMachineScheduler.h.

References llvm::ScheduleDAGMI::CurrentTop.

◆ getEntrySU()

SUnit & llvm::SIScheduleDAGMI::getEntrySU ( )

inline

Definition at line 455 of file SIMachineScheduler.h.

References llvm::ScheduleDAG::EntrySU.

◆ getExitSU()

SUnit & llvm::SIScheduleDAGMI::getExitSU ( )

inline

Definition at line 456 of file SIMachineScheduler.h.

References llvm::ScheduleDAG::ExitSU.

◆ getInRegs()

std::set< unsigned > llvm::SIScheduleDAGMI::getInRegs ( )

inline

Definition at line 465 of file SIMachineScheduler.h.

References llvm::RegPressureTracker::getPressure(), llvm::RegisterPressure::LiveInRegs, and llvm::ScheduleDAGMILive::RPTracker.

Referenced by llvm::SIScheduleBlockScheduler::SIScheduleBlockScheduler().

◆ getLIS()

LiveIntervals * llvm::SIScheduleDAGMI::getLIS ( )

inline

Definition at line 451 of file SIMachineScheduler.h.

References llvm::ScheduleDAGMI::LIS.

◆ getMRI()

MachineRegisterInfo * llvm::SIScheduleDAGMI::getMRI ( )

inline

Definition at line 452 of file SIMachineScheduler.h.

References llvm::ScheduleDAG::MRI.

◆ getOutRegs()

std::set< unsigned > llvm::SIScheduleDAGMI::getOutRegs ( )

inline

Definition at line 473 of file SIMachineScheduler.h.

References llvm::RegPressureTracker::getPressure(), llvm::RegisterPressure::LiveOutRegs, and llvm::ScheduleDAGMILive::RPTracker.

Referenced by llvm::SIScheduleBlockScheduler::SIScheduleBlockScheduler().

◆ GetTopo()

ScheduleDAGTopologicalSort * llvm::SIScheduleDAGMI::GetTopo ( )

inline

Definition at line 454 of file SIMachineScheduler.h.

References llvm::ScheduleDAGInstrs::Topo.

◆ getTRI()

const TargetRegisterInfo * llvm::SIScheduleDAGMI::getTRI ( )

inline

Definition at line 453 of file SIMachineScheduler.h.

References llvm::ScheduleDAG::TRI.

Referenced by llvm::SIScheduleBlock::printDebug().

◆ initRPTracker()

void llvm::SIScheduleDAGMI::initRPTracker ( RegPressureTracker & RPTracker )

inline

Definition at line 444 of file SIMachineScheduler.h.

References llvm::ScheduleDAGInstrs::BB, llvm::RegPressureTracker::init(), llvm::ScheduleDAGMI::LIS, llvm::ScheduleDAG::MF, llvm::ScheduleDAGMILive::RegClassInfo, llvm::ScheduleDAGInstrs::RegionBegin, and llvm::ScheduleDAGMILive::RPTracker.

◆ restoreSULinksLeft()

void SIScheduleDAGMI::restoreSULinksLeft ( )

Definition at line 1837 of file SIMachineScheduler.cpp.

References llvm::ScheduleDAG::SUnits.

◆ schedule()

void SIScheduleDAGMI::schedule ( )

overridevirtual

Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.

schedule - Called back from MachineScheduler::runOnMachineFunction after setting up the current scheduling region.

[RegionBegin, RegionEnd) only includes instructions that have DAG nodes, not scheduling boundaries.

This is a skeletal driver, with all the functionality pushed into helpers, so that it can be easily extended by experimental schedulers. Generally, implementing MachineSchedStrategy should be sufficient to implement a new scheduling algorithm. However, if a scheduler further subclasses ScheduleDAGMILive then it will want to override this virtual method in order to update any specialized state.

Reimplemented from llvm::ScheduleDAGMILive.

Definition at line 1868 of file SIMachineScheduler.cpp.

Member Data Documentation

◆ BottomUpIndex2SU

std::vector<int> llvm::SIScheduleDAGMI::BottomUpIndex2SU

Definition at line 494 of file SIMachineScheduler.h.

◆ IsHighLatencySU

std::vector<unsigned> llvm::SIScheduleDAGMI::IsHighLatencySU

Definition at line 490 of file SIMachineScheduler.h.

Referenced by llvm::SIScheduleBlock::finalizeUnits(), and schedule().

◆ IsLowLatencySU

std::vector<unsigned> llvm::SIScheduleDAGMI::IsLowLatencySU

Definition at line 488 of file SIMachineScheduler.h.

Referenced by schedule().

◆ LowLatencyOffset

std::vector<unsigned> llvm::SIScheduleDAGMI::LowLatencyOffset

Definition at line 489 of file SIMachineScheduler.h.

Referenced by schedule().

◆ TopDownIndex2SU

std::vector<int> llvm::SIScheduleDAGMI::TopDownIndex2SU

Definition at line 493 of file SIMachineScheduler.h.

The documentation for this class was generated from the following files:

lib/Target/AMDGPU/SIMachineScheduler.h
lib/Target/AMDGPU/SIMachineScheduler.cpp

Public Member Functions

Public Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ SIScheduleDAGMI()

◆ ~SIScheduleDAGMI()

Member Function Documentation

◆ fillVgprSgprCost()

◆ getBB()

◆ getCurrentBottom()

◆ getCurrentTop()

◆ getEntrySU()

◆ getExitSU()

◆ getInRegs()

◆ getLIS()

◆ getMRI()

◆ getOutRegs()

◆ GetTopo()

◆ getTRI()

◆ initRPTracker()

◆ restoreSULinksLeft()

◆ schedule()

Member Data Documentation

◆ BottomUpIndex2SU

◆ IsHighLatencySU

◆ IsLowLatencySU

◆ LowLatencyOffset

◆ TopDownIndex2SU