#include "Target/ARM/ThumbRegisterInfo.h"

Inheritance diagram for llvm::ThumbRegisterInfo:

Public Member Functions
	ThumbRegisterInfo ()

const TargetRegisterClass *	getLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &MF) const override

const TargetRegisterClass *	getPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override

void	emitLoadConstPool (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const override
	emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.

bool	rewriteFrameIndex (MachineBasicBlock::iterator II, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII) const

void	resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const override

bool	eliminateFrameIndex (MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

bool	useFPForScavengingIndex (const MachineFunction &MF) const override

Public Member Functions inherited from llvm::ARMBaseRegisterInfo
const MCPhysReg *	getCalleeSavedRegs (const MachineFunction *MF) const override
	Code Generation virtual methods...

const MCPhysReg *	getCalleeSavedRegsViaCopy (const MachineFunction *MF) const

const uint32_t *	getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override

const uint32_t *	getNoPreservedMask () const override

const uint32_t *	getTLSCallPreservedMask (const MachineFunction &MF) const

const uint32_t *	getSjLjDispatchPreservedMask (const MachineFunction &MF) const

const uint32_t *	getThisReturnPreservedMask (const MachineFunction &MF, CallingConv::ID) const
	getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on an i32 first argument if the calling convention is one that can (partially) model this attribute with a preserved mask (i.e.

ArrayRef< MCPhysReg >	getIntraCallClobberedRegs (const MachineFunction *MF) const override

BitVector	getReservedRegs (const MachineFunction &MF) const override

bool	isAsmClobberable (const MachineFunction &MF, MCRegister PhysReg) const override

bool	isInlineAsmReadOnlyReg (const MachineFunction &MF, unsigned PhysReg) const override

const TargetRegisterClass *	getPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override

const TargetRegisterClass *	getCrossCopyRegClass (const TargetRegisterClass *RC) const override

const TargetRegisterClass *	getLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &MF) const override

unsigned	getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override

bool	getRegAllocationHints (Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap VRM, const LiveRegMatrix Matrix) const override

void	updateRegAllocHint (Register Reg, Register NewReg, MachineFunction &MF) const override

bool	hasBasePointer (const MachineFunction &MF) const

bool	canRealignStack (const MachineFunction &MF) const override

int64_t	getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override

bool	needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
	needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP.

Register	materializeFrameBaseRegister (MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
	materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic block.

void	resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const override

bool	isFrameOffsetLegal (const MachineInstr *MI, Register BaseReg, int64_t Offset) const override

bool	cannotEliminateFrame (const MachineFunction &MF) const

Register	getFrameRegister (const MachineFunction &MF) const override

Register	getBaseRegister () const

virtual void	emitLoadConstPool (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const
	emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.

bool	requiresRegisterScavenging (const MachineFunction &MF) const override
	Code Generation virtual methods...

bool	requiresFrameIndexScavenging (const MachineFunction &MF) const override

bool	requiresVirtualBaseRegisters (const MachineFunction &MF) const override

bool	eliminateFrameIndex (MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

bool	shouldCoalesce (MachineInstr MI, const TargetRegisterClass SrcRC, unsigned SubReg, const TargetRegisterClass DstRC, unsigned DstSubReg, const TargetRegisterClass NewRC, LiveIntervals &LIS) const override
	SrcRC and DstRC will be morphed into NewRC if this returns true.

bool	shouldRewriteCopySrc (const TargetRegisterClass DefRC, unsigned DefSubReg, const TargetRegisterClass SrcRC, unsigned SrcSubReg) const override

int	getSEHRegNum (unsigned i) const

Additional Inherited Members
Protected Member Functions inherited from llvm::ARMBaseRegisterInfo
	ARMBaseRegisterInfo ()

Protected Attributes inherited from llvm::ARMBaseRegisterInfo
unsigned	BasePtr = ARM::R6
	BasePtr - ARM physical register used as a base ptr in complex stack frames.

Detailed Description

Definition at line 25 of file ThumbRegisterInfo.h.

Constructor & Destructor Documentation

◆ ThumbRegisterInfo()

ThumbRegisterInfo::ThumbRegisterInfo ( )

default

Member Function Documentation

◆ eliminateFrameIndex()

bool ThumbRegisterInfo::eliminateFrameIndex	(	MachineBasicBlock::iterator	II,
		int	SPAdj,
		unsigned	FIOperandNum,
		RegScavenger *	RS = `nullptr`
	)		const

override

Definition at line 539 of file ThumbRegisterInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), contains(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitLoadConstPool(), llvm::emitThumbRegPlusImmediate(), emitThumbRegPlusImmInReg(), llvm::MachineFunction::getFrameInfo(), llvm::ARMSubtarget::getFrameLowering(), llvm::MachineFunction::getInfo(), llvm::ARMSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::ARMFrameLowering::hasReservedCallFrame(), llvm::MachineFrameInfo::hasVarSizedObjects(), II, llvm::RegScavenger::isScavengingFrameIndex(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMFunctionInfo::isThumbFunction(), llvm_unreachable, MBB, MI, llvm::Offset, llvm::predOps(), removeOperands(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), rewriteFrameIndex(), and TII.

◆ emitLoadConstPool()

void ThumbRegisterInfo::emitLoadConstPool	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator &	MBBI,
		const DebugLoc &	dl,
		Register	DestReg,
		unsigned	SubIdx,
		int	Val,
		ARMCC::CondCodes	Pred = `ARMCC::AL`,
		Register	PredReg = `Register()`,
		unsigned	MIFlags = `MachineInstr::NoFlags`
	)		const

overridevirtual

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.

Reimplemented from llvm::ARMBaseRegisterInfo.

Definition at line 101 of file ThumbRegisterInfo.cpp.

References assert(), emitThumb1LoadConstPool(), emitThumb2LoadConstPool(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::isARMLowRegister(), llvm::ARMSubtarget::isThumb1Only(), llvm::Register::isVirtual(), MBB, and MBBI.

Referenced by eliminateFrameIndex().

◆ getLargestLegalSuperClass()

const TargetRegisterClass * ThumbRegisterInfo::getLargestLegalSuperClass	(	const TargetRegisterClass *	RC,
		const MachineFunction &	MF
	)		const

override

Definition at line 41 of file ThumbRegisterInfo.cpp.

References llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::MachineFunction::getSubtarget(), and llvm::ARMSubtarget::isThumb1Only().

◆ getPointerRegClass()

const TargetRegisterClass * ThumbRegisterInfo::getPointerRegClass	(	const MachineFunction &	MF,
		unsigned	Kind = `0`
	)		const

override

Definition at line 52 of file ThumbRegisterInfo.cpp.

References llvm::ARMBaseRegisterInfo::getPointerRegClass(), llvm::MachineFunction::getSubtarget(), and llvm::ARMSubtarget::isThumb1Only().

◆ resolveFrameIndex()

void ThumbRegisterInfo::resolveFrameIndex	(	MachineInstr &	MI,
		Register	BaseReg,
		int64_t	Offset
	)		const

override

Definition at line 519 of file ThumbRegisterInfo.cpp.

References assert(), llvm::Done, llvm::ARMSubtarget::getInstrInfo(), llvm::MachineFunction::getSubtarget(), llvm::ARMSubtarget::isThumb1Only(), MI, llvm::Offset, llvm::ARMBaseRegisterInfo::resolveFrameIndex(), rewriteFrameIndex(), and TII.

◆ rewriteFrameIndex()

bool ThumbRegisterInfo::rewriteFrameIndex	(	MachineBasicBlock::iterator	II,
		unsigned	FrameRegIdx,
		Register	FrameReg,
		int &	Offset,
		const ARMBaseInstrInfo &	TII
	)		const

◆ useFPForScavengingIndex()

bool ThumbRegisterInfo::useFPForScavengingIndex ( const MachineFunction & MF ) const

override

Definition at line 681 of file ThumbRegisterInfo.cpp.

References llvm::MachineFunction::getSubtarget(), and llvm::ARMSubtarget::isThumb1Only().

The documentation for this struct was generated from the following files:

lib/Target/ARM/ThumbRegisterInfo.h
lib/Target/ARM/ThumbRegisterInfo.cpp

Public Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ ThumbRegisterInfo()

Member Function Documentation

◆ eliminateFrameIndex()

◆ emitLoadConstPool()

◆ getLargestLegalSuperClass()

◆ getPointerRegClass()

◆ resolveFrameIndex()

◆ rewriteFrameIndex()

◆ useFPForScavengingIndex()