LLVM  12.0.0git
BPFAsmBackend.cpp
Go to the documentation of this file.
1 //===-- BPFAsmBackend.cpp - BPF Assembler Backend -------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/ADT/StringRef.h"
11 #include "llvm/MC/MCAsmBackend.h"
12 #include "llvm/MC/MCAssembler.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCFixup.h"
15 #include "llvm/MC/MCObjectWriter.h"
17 #include <cassert>
18 #include <cstdint>
19 
20 using namespace llvm;
21 
22 namespace {
23 
24 class BPFAsmBackend : public MCAsmBackend {
25 public:
26  BPFAsmBackend(support::endianness Endian) : MCAsmBackend(Endian) {}
27  ~BPFAsmBackend() override = default;
28 
29  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
31  uint64_t Value, bool IsResolved,
32  const MCSubtargetInfo *STI) const override;
33 
34  std::unique_ptr<MCObjectTargetWriter>
35  createObjectTargetWriter() const override;
36 
37  // No instruction requires relaxation
38  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
39  const MCRelaxableFragment *DF,
40  const MCAsmLayout &Layout) const override {
41  return false;
42  }
43 
44  unsigned getNumFixupKinds() const override { return 1; }
45 
46  bool mayNeedRelaxation(const MCInst &Inst,
47  const MCSubtargetInfo &STI) const override {
48  return false;
49  }
50 
51  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
52 };
53 
54 } // end anonymous namespace
55 
56 bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
57  if ((Count % 8) != 0)
58  return false;
59 
60  for (uint64_t i = 0; i < Count; i += 8)
61  support::endian::write<uint64_t>(OS, 0x15000000, Endian);
62 
63  return true;
64 }
65 
66 void BPFAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
67  const MCValue &Target,
69  bool IsResolved,
70  const MCSubtargetInfo *STI) const {
71  if (Fixup.getKind() == FK_SecRel_4 || Fixup.getKind() == FK_SecRel_8) {
72  // The Value is 0 for global variables, and the in-section offset
73  // for static variables. Write to the immediate field of the inst.
74  assert(Value <= UINT32_MAX);
75  support::endian::write<uint32_t>(&Data[Fixup.getOffset() + 4],
76  static_cast<uint32_t>(Value),
77  Endian);
78  } else if (Fixup.getKind() == FK_Data_4) {
79  support::endian::write<uint32_t>(&Data[Fixup.getOffset()], Value, Endian);
80  } else if (Fixup.getKind() == FK_Data_8) {
81  support::endian::write<uint64_t>(&Data[Fixup.getOffset()], Value, Endian);
82  } else if (Fixup.getKind() == FK_PCRel_4) {
83  Value = (uint32_t)((Value - 8) / 8);
84  if (Endian == support::little) {
85  Data[Fixup.getOffset() + 1] = 0x10;
86  support::endian::write32le(&Data[Fixup.getOffset() + 4], Value);
87  } else {
88  Data[Fixup.getOffset() + 1] = 0x1;
89  support::endian::write32be(&Data[Fixup.getOffset() + 4], Value);
90  }
91  } else {
92  assert(Fixup.getKind() == FK_PCRel_2);
93  Value = (uint16_t)((Value - 8) / 8);
94  support::endian::write<uint16_t>(&Data[Fixup.getOffset() + 2], Value,
95  Endian);
96  }
97 }
98 
99 std::unique_ptr<MCObjectTargetWriter>
100 BPFAsmBackend::createObjectTargetWriter() const {
101  return createBPFELFObjectWriter(0);
102 }
103 
105  const MCSubtargetInfo &STI,
106  const MCRegisterInfo &MRI,
107  const MCTargetOptions &) {
108  return new BPFAsmBackend(support::little);
109 }
110 
112  const MCSubtargetInfo &STI,
113  const MCRegisterInfo &MRI,
114  const MCTargetOptions &) {
115  return new BPFAsmBackend(support::big);
116 }
void write32be(void *P, uint32_t V)
Definition: Endian.h:419
This class represents lattice values for constants.
Definition: AllocatorList.h:23
std::unique_ptr< MCObjectTargetWriter > createBPFELFObjectWriter(uint8_t OSABI)
This represents an "assembler immediate".
Definition: MCValue.h:37
void write32le(void *P, uint32_t V)
Definition: Endian.h:416
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:82
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
A four-byte section relative fixup.
Definition: MCFixup.h:43
A four-byte fixup.
Definition: MCFixup.h:26
MCAsmBackend * createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:261
unsigned const MachineRegisterInfo * MRI
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:298
uint32_t getOffset() const
Definition: MCFixup.h:135
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
A two-byte pc relative fixup.
Definition: MCFixup.h:30
A four-byte pc relative fixup.
Definition: MCFixup.h:31
MCAsmBackend * createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target - Wrapper for Target specific information.
A eight-byte section relative fixup.
Definition: MCFixup.h:44
Generic base class for all target subtargets.
A eight-byte fixup.
Definition: MCFixup.h:27
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:74
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
MCFixupKind getKind() const
Definition: MCFixup.h:131