LLVM  14.0.0git
HexagonMachineScheduler.h
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1 //===- HexagonMachineScheduler.h - Custom Hexagon MI scheduler --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Custom Hexagon MI scheduler.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
15 
20 
21 namespace llvm {
22 
23 class SUnit;
24 
26 public:
28  bool hasDependence(const SUnit *SUd, const SUnit *SUu) override;
29 };
30 
32 protected:
35  const TargetSchedModel *SchedModel) const override;
36  int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate,
37  RegPressureDelta &Delta, bool verbose) override;
38 };
39 
40 } // end namespace llvm
41 
42 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::VLIWResourceModel::VLIWResourceModel
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
Definition: VLIWMachineScheduler.cpp:67
llvm::ConvergingVLIWScheduler::SchedCandidate
Store the state used by ConvergingVLIWScheduler heuristics, required for the lifetime of one invocati...
Definition: VLIWMachineScheduler.h:92
llvm::HexagonConvergingVLIWScheduler::createVLIWResourceModel
VLIWResourceModel * createVLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const override
Definition: HexagonMachineScheduler.cpp:40
llvm::HexagonConvergingVLIWScheduler
Definition: HexagonMachineScheduler.h:31
RegisterPressure.h
llvm::VLIWResourceModel
Definition: VLIWMachineScheduler.h:31
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::ConvergingVLIWScheduler
Definition: VLIWMachineScheduler.h:88
TargetSubtargetInfo.h
llvm::HexagonVLIWResourceModel
Definition: HexagonMachineScheduler.h:25
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::RegPressureDelta
Store the effects of a change in pressure on things that MI scheduler cares about.
Definition: RegisterPressure.h:239
VLIWMachineScheduler.h
llvm::ConvergingVLIWScheduler::SchedModel
const TargetSchedModel * SchedModel
Definition: VLIWMachineScheduler.h:208
MachineScheduler.h
llvm::HexagonConvergingVLIWScheduler::SchedulingCost
int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) override
Single point to compute overall scheduling cost.
Definition: HexagonMachineScheduler.cpp:45
llvm::HexagonVLIWResourceModel::hasDependence
bool hasDependence(const SUnit *SUd, const SUnit *SUu) override
Return true if there is a dependence between SUd and SUu.
Definition: HexagonMachineScheduler.cpp:26
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::ReadyQueue
Helpers for implementing custom MachineSchedStrategy classes.
Definition: MachineScheduler.h:532