LLVM  16.0.0git
VLIWMachineScheduler.h
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1 //===- VLIWMachineScheduler.h - VLIW-Focused Scheduling Pass ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 // //
9 //===----------------------------------------------------------------------===//
10 
11 #ifndef LLVM_CODEGEN_VLIWMACHINESCHEDULER_H
12 #define LLVM_CODEGEN_VLIWMACHINESCHEDULER_H
13 
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/Twine.h"
18 #include <limits>
19 #include <memory>
20 #include <utility>
21 
22 namespace llvm {
23 
24 class DFAPacketizer;
25 class RegisterClassInfo;
26 class ScheduleHazardRecognizer;
27 class SUnit;
28 class TargetInstrInfo;
29 class TargetSubtargetInfo;
30 
32 protected:
34 
35  /// ResourcesModel - Represents VLIW state.
36  /// Not limited to VLIW targets per se, but assumes definition of resource
37  /// model by a target.
39 
41 
42  /// Local packet/bundle model. Purely
43  /// internal to the MI scheduler at the time.
45 
46  /// Total packets created.
47  unsigned TotalPackets = 0;
48 
49 public:
51 
52  virtual ~VLIWResourceModel();
53 
54  virtual void reset();
55 
56  virtual bool hasDependence(const SUnit *SUd, const SUnit *SUu);
57  virtual bool isResourceAvailable(SUnit *SU, bool IsTop);
58  virtual bool reserveResources(SUnit *SU, bool IsTop);
59  unsigned getTotalPackets() const { return TotalPackets; }
60  size_t getPacketInstCount() const { return Packet.size(); }
61  bool isInPacket(SUnit *SU) const { return is_contained(Packet, SU); }
62 
63 protected:
64  virtual DFAPacketizer *createPacketizer(const TargetSubtargetInfo &STI) const;
65 };
66 
67 /// Extend the standard ScheduleDAGMILive to provide more context and override
68 /// the top-level schedule() driver.
70 public:
72  std::unique_ptr<MachineSchedStrategy> S)
73  : ScheduleDAGMILive(C, std::move(S)) {}
74 
75  /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
76  /// time to do some work.
77  void schedule() override;
78 
80  int getBBSize() { return BB->size(); }
81 };
82 
83 //===----------------------------------------------------------------------===//
84 // ConvergingVLIWScheduler - Implementation of a VLIW-aware
85 // MachineSchedStrategy.
86 //===----------------------------------------------------------------------===//
87 
89 protected:
90  /// Store the state used by ConvergingVLIWScheduler heuristics, required
91  /// for the lifetime of one invocation of pickNode().
92  struct SchedCandidate {
93  // The best SUnit candidate.
94  SUnit *SU = nullptr;
95 
96  // Register pressure values for the best candidate.
98 
99  // Best scheduling cost.
100  int SCost = 0;
101 
102  SchedCandidate() = default;
103  };
104  /// Represent the type of SchedCandidate found within a single queue.
105  enum CandResult {
114  };
115 
116  // Constants used to denote relative importance of
117  // heuristic components for cost computation.
118  static constexpr unsigned PriorityOne = 200;
119  static constexpr unsigned PriorityTwo = 50;
120  static constexpr unsigned PriorityThree = 75;
121  static constexpr unsigned ScaleTwo = 10;
122 
123  /// Each Scheduling boundary is associated with ready queues. It tracks the
124  /// current cycle in whichever direction at has moved, and maintains the state
125  /// of "hazards" and other interlocks at the current cycle.
128  const TargetSchedModel *SchedModel = nullptr;
129 
132  bool CheckPending = false;
133 
136 
137  unsigned CurrCycle = 0;
138  unsigned IssueCount = 0;
139  unsigned CriticalPathLength = 0;
140 
141  /// MinReadyCycle - Cycle of the soonest available instruction.
143 
144  // Remember the greatest min operand latency.
145  unsigned MaxMinLatency = 0;
146 
147  /// Pending queues extend the ready queues with the same ID and the
148  /// PendingFlag set.
149  VLIWSchedBoundary(unsigned ID, const Twine &Name)
150  : Available(ID, Name + ".A"),
151  Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name + ".P") {}
152 
154 
155  void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
156  DAG = dag;
157  SchedModel = smodel;
158  CurrCycle = 0;
159  IssueCount = 0;
160  // Initialize the critical path length limit, which used by the scheduling
161  // cost model to determine the value for scheduling an instruction. We use
162  // a slightly different heuristic for small and large functions. For small
163  // functions, it's important to use the height/depth of the instruction.
164  // For large functions, prioritizing by height or depth increases spills.
166  if (DAG->getBBSize() < 50)
167  // We divide by two as a cheap and simple heuristic to reduce the
168  // critcal path length, which increases the priority of using the graph
169  // height/depth in the scheduler's cost computation.
170  CriticalPathLength >>= 1;
171  else {
172  // For large basic blocks, we prefer a larger critical path length to
173  // decrease the priority of using the graph height/depth.
174  unsigned MaxPath = 0;
175  for (auto &SU : DAG->SUnits)
176  MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth());
178  }
179  }
180 
181  bool isTop() const {
183  }
184 
185  bool checkHazard(SUnit *SU);
186 
187  void releaseNode(SUnit *SU, unsigned ReadyCycle);
188 
189  void bumpCycle();
190 
191  void bumpNode(SUnit *SU);
192 
193  void releasePending();
194 
195  void removeReady(SUnit *SU);
196 
198 
199  bool isLatencyBound(SUnit *SU) {
201  return true;
202  unsigned PathLength = isTop() ? SU->getHeight() : SU->getDepth();
203  return CriticalPathLength - CurrCycle <= PathLength;
204  }
205  };
206 
208  const TargetSchedModel *SchedModel = nullptr;
209 
210  // State of the top and bottom scheduled instruction boundaries.
213 
214  /// List of pressure sets that have a high pressure level in the region.
216 
217 public:
218  /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
219  enum { TopQID = 1, BotQID = 2, LogMaxQID = 2 };
220 
221  ConvergingVLIWScheduler() : Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
222  virtual ~ConvergingVLIWScheduler() = default;
223 
224  void initialize(ScheduleDAGMI *dag) override;
225 
226  SUnit *pickNode(bool &IsTopNode) override;
227 
228  void schedNode(SUnit *SU, bool IsTopNode) override;
229 
230  void releaseTopNode(SUnit *SU) override;
231 
232  void releaseBottomNode(SUnit *SU) override;
233 
234  unsigned reportPackets() {
235  return Top.ResourceModel->getTotalPackets() +
237  }
238 
239 protected:
240  virtual VLIWResourceModel *
242  const TargetSchedModel *SchedModel) const;
243 
244  SUnit *pickNodeBidrectional(bool &IsTopNode);
245 
246  int pressureChange(const SUnit *SU, bool isBotUp);
247 
248  virtual int SchedulingCost(ReadyQueue &Q, SUnit *SU,
249  SchedCandidate &Candidate, RegPressureDelta &Delta,
250  bool verbose);
251 
252  CandResult pickNodeFromQueue(VLIWSchedBoundary &Zone,
253  const RegPressureTracker &RPTracker,
254  SchedCandidate &Candidate);
255 #ifndef NDEBUG
256  void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
257  int Cost, PressureChange P = PressureChange());
258 
259  void readyQueueVerboseDump(const RegPressureTracker &RPTracker,
260  SchedCandidate &Candidate, ReadyQueue &Q);
261 #endif
262 };
263 
264 ScheduleDAGMILive *createVLIWSched(MachineSchedContext *C);
265 
266 } // end namespace llvm
267 
268 #endif // LLVM_CODEGEN_VLIWMACHINESCHEDULER_H
llvm::ConvergingVLIWScheduler::initialize
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
Definition: VLIWMachineScheduler.cpp:270
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::VLIWMachineScheduler::getRegClassInfo
RegisterClassInfo * getRegClassInfo()
Definition: VLIWMachineScheduler.h:79
llvm::ConvergingVLIWScheduler::pickNode
SUnit * pickNode(bool &IsTopNode) override
Pick the best node to balance the schedule. Implements MachineSchedStrategy.
Definition: VLIWMachineScheduler.cpp:950
llvm::ConvergingVLIWScheduler::pickNodeBidrectional
SUnit * pickNodeBidrectional(bool &IsTopNode)
Pick the best candidate node from either the top or bottom queue.
Definition: VLIWMachineScheduler.cpp:884
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::MaxMinLatency
unsigned MaxMinLatency
Definition: VLIWMachineScheduler.h:145
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::ConvergingVLIWScheduler::readyQueueVerboseDump
void readyQueueVerboseDump(const RegPressureTracker &RPTracker, SchedCandidate &Candidate, ReadyQueue &Q)
Definition: VLIWMachineScheduler.cpp:524
llvm::VLIWResourceModel::VLIWResourceModel
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
Definition: VLIWMachineScheduler.cpp:65
llvm::ConvergingVLIWScheduler::SingleExcess
@ SingleExcess
Definition: VLIWMachineScheduler.h:108
llvm::ConvergingVLIWScheduler::SchedCandidate
Store the state used by ConvergingVLIWScheduler heuristics, required for the lifetime of one invocati...
Definition: VLIWMachineScheduler.h:92
llvm::VLIWResourceModel::hasDependence
virtual bool hasDependence(const SUnit *SUd, const SUnit *SUu)
Return true if there is a dependence between SUd and SUu.
Definition: VLIWMachineScheduler.cpp:87
llvm::ConvergingVLIWScheduler::HighPressureSets
SmallVector< bool > HighPressureSets
List of pressure sets that have a high pressure level in the region.
Definition: VLIWMachineScheduler.h:215
llvm::RegPressureTracker
Track the current register pressure at some position in the instruction stream, and remember the high...
Definition: RegisterPressure.h:357
llvm::VLIWMachineScheduler
Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...
Definition: VLIWMachineScheduler.h:69
llvm::ConvergingVLIWScheduler::SingleMax
@ SingleMax
Definition: VLIWMachineScheduler.h:110
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::VLIWSchedBoundary
VLIWSchedBoundary(unsigned ID, const Twine &Name)
Pending queues extend the ready queues with the same ID and the PendingFlag set.
Definition: VLIWMachineScheduler.h:149
llvm::SUnit::getDepth
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
Definition: ScheduleDAG.h:398
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::ConvergingVLIWScheduler::PriorityOne
static constexpr unsigned PriorityOne
Definition: VLIWMachineScheduler.h:118
llvm::ConvergingVLIWScheduler::ConvergingVLIWScheduler
ConvergingVLIWScheduler()
Definition: VLIWMachineScheduler.h:221
llvm::ConvergingVLIWScheduler::BotQID
@ BotQID
Definition: VLIWMachineScheduler.h:219
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::SchedModel
const TargetSchedModel * SchedModel
Definition: VLIWMachineScheduler.h:128
llvm::ConvergingVLIWScheduler::PriorityTwo
static constexpr unsigned PriorityTwo
Definition: VLIWMachineScheduler.h:119
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::CriticalPathLength
unsigned CriticalPathLength
Definition: VLIWMachineScheduler.h:139
llvm::ConvergingVLIWScheduler::traceCandidate
void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P=PressureChange())
Definition: VLIWMachineScheduler.cpp:510
llvm::ConvergingVLIWScheduler::releaseBottomNode
void releaseBottomNode(SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
Definition: VLIWMachineScheduler.cpp:325
llvm::ConvergingVLIWScheduler::TopQID
@ TopQID
Definition: VLIWMachineScheduler.h:219
llvm::MachineSchedStrategy
MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.
Definition: MachineScheduler.h:208
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::TargetSchedModel::getIssueWidth
unsigned getIssueWidth() const
Maximum number of micro-ops that may be scheduled per cycle.
Definition: TargetSchedule.h:98
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
Twine.h
llvm::ConvergingVLIWScheduler::pressureChange
int pressureChange(const SUnit *SU, bool isBotUp)
Check if the instruction changes the register pressure of a register in the high pressure set.
Definition: VLIWMachineScheduler.cpp:580
llvm::ConvergingVLIWScheduler::NoCand
@ NoCand
Definition: VLIWMachineScheduler.h:106
llvm::ReadyQueue::getID
unsigned getID() const
Definition: MachineScheduler.h:542
llvm::DFAPacketizer
Definition: DFAPacketizer.h:48
llvm::VLIWResourceModel::TII
const TargetInstrInfo * TII
Definition: VLIWMachineScheduler.h:33
llvm::ConvergingVLIWScheduler::Bot
VLIWSchedBoundary Bot
Definition: VLIWMachineScheduler.h:212
llvm::VLIWResourceModel::reset
virtual void reset()
Definition: VLIWMachineScheduler.cpp:79
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ConvergingVLIWScheduler::Top
VLIWSchedBoundary Top
Definition: VLIWMachineScheduler.h:211
llvm::ConvergingVLIWScheduler::NodeOrder
@ NodeOrder
Definition: VLIWMachineScheduler.h:107
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::isTop
bool isTop() const
Definition: VLIWMachineScheduler.h:181
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::IssueCount
unsigned IssueCount
Definition: VLIWMachineScheduler.h:138
llvm::ConvergingVLIWScheduler::CandResult
CandResult
Represent the type of SchedCandidate found within a single queue.
Definition: VLIWMachineScheduler.h:105
llvm::ConvergingVLIWScheduler::Weak
@ Weak
Definition: VLIWMachineScheduler.h:113
llvm::SUnit::getHeight
unsigned getHeight() const
Returns the height of this node, which is the length of the maximum path down to any node which has n...
Definition: ScheduleDAG.h:406
llvm::ScheduleDAGMILive::RegClassInfo
RegisterClassInfo * RegClassInfo
Definition: MachineScheduler.h:394
llvm::VLIWResourceModel
Definition: VLIWMachineScheduler.h:31
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::checkHazard
bool checkHazard(SUnit *SU)
Does this SU have a hazard within the current instruction group.
Definition: VLIWMachineScheduler.cpp:361
llvm::ConvergingVLIWScheduler::LogMaxQID
@ LogMaxQID
Definition: VLIWMachineScheduler.h:219
llvm::VLIWMachineScheduler::schedule
void schedule() override
Schedule - This is called back from ScheduleDAGInstrs::Run() when it's time to do some work.
Definition: VLIWMachineScheduler.cpp:201
llvm::VLIWResourceModel::isResourceAvailable
virtual bool isResourceAvailable(SUnit *SU, bool IsTop)
Check if scheduling of this SU is possible in the current packet.
Definition: VLIWMachineScheduler.cpp:108
llvm::VLIWResourceModel::ResourcesModel
DFAPacketizer * ResourcesModel
ResourcesModel - Represents VLIW state.
Definition: VLIWMachineScheduler.h:38
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::HazardRec
ScheduleHazardRecognizer * HazardRec
Definition: VLIWMachineScheduler.h:134
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::Pending
ReadyQueue Pending
Definition: VLIWMachineScheduler.h:131
TargetSchedule.h
llvm::VLIWResourceModel::isInPacket
bool isInPacket(SUnit *SU) const
Definition: VLIWMachineScheduler.h:61
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::VLIWResourceModel::getTotalPackets
unsigned getTotalPackets() const
Definition: VLIWMachineScheduler.h:59
llvm::ConvergingVLIWScheduler::SchedulingCost
virtual int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)
Single point to compute overall scheduling cost.
Definition: VLIWMachineScheduler.cpp:596
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:127
llvm::VLIWMachineScheduler::getBBSize
int getBBSize()
Definition: VLIWMachineScheduler.h:80
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::bumpNode
void bumpNode(SUnit *SU)
Move the boundary of scheduled code by one SUnit.
Definition: VLIWMachineScheduler.cpp:414
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1868
llvm::ConvergingVLIWScheduler
Definition: VLIWMachineScheduler.h:88
llvm::VLIWResourceModel::reserveResources
virtual bool reserveResources(SUnit *SU, bool IsTop)
Keep track of available resources.
Definition: VLIWMachineScheduler.cpp:145
llvm::ConvergingVLIWScheduler::ScaleTwo
static constexpr unsigned ScaleTwo
Definition: VLIWMachineScheduler.h:121
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1861
llvm::MachineBasicBlock::size
unsigned size() const
Definition: MachineBasicBlock.h:275
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary
Each Scheduling boundary is associated with ready queues.
Definition: VLIWMachineScheduler.h:126
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::releasePending
void releasePending()
Release pending ready nodes in to the available queue.
Definition: VLIWMachineScheduler.cpp:443
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:273
llvm::VLIWResourceModel::Packet
SmallVector< SUnit * > Packet
Local packet/bundle model.
Definition: VLIWMachineScheduler.h:44
llvm::createVLIWSched
ScheduleDAGMILive * createVLIWSched(MachineSchedContext *C)
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::CurrCycle
unsigned CurrCycle
Definition: VLIWMachineScheduler.h:137
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::DAG
VLIWMachineScheduler * DAG
Definition: VLIWMachineScheduler.h:127
llvm::ConvergingVLIWScheduler::DAG
VLIWMachineScheduler * DAG
Definition: VLIWMachineScheduler.h:207
llvm::ConvergingVLIWScheduler::BestCost
@ BestCost
Definition: VLIWMachineScheduler.h:112
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
llvm::VLIWResourceModel::TotalPackets
unsigned TotalPackets
Total packets created.
Definition: VLIWMachineScheduler.h:47
llvm::VLIWResourceModel::SchedModel
const TargetSchedModel * SchedModel
Definition: VLIWMachineScheduler.h:40
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::ResourceModel
VLIWResourceModel * ResourceModel
Definition: VLIWMachineScheduler.h:135
llvm::RegPressureDelta
Store the effects of a change in pressure on things that MI scheduler cares about.
Definition: RegisterPressure.h:238
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:561
std
Definition: BitVector.h:851
llvm::ConvergingVLIWScheduler::schedNode
void schedNode(SUnit *SU, bool IsTopNode) override
Update the scheduler's state after scheduling a node.
Definition: VLIWMachineScheduler.cpp:999
llvm::ConvergingVLIWScheduler::SchedCandidate::SchedCandidate
SchedCandidate()=default
llvm::VLIWResourceModel::~VLIWResourceModel
virtual ~VLIWResourceModel()
Definition: VLIWMachineScheduler.cpp:84
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::Available
ReadyQueue Available
Definition: VLIWMachineScheduler.h:130
llvm::PressureChange
Capture a change in pressure for a single pressure set.
Definition: RegisterPressure.h:102
llvm::ConvergingVLIWScheduler::SingleCritical
@ SingleCritical
Definition: VLIWMachineScheduler.h:109
llvm::ConvergingVLIWScheduler::reportPackets
unsigned reportPackets()
Definition: VLIWMachineScheduler.h:234
llvm::ConvergingVLIWScheduler::SchedCandidate::SCost
int SCost
Definition: VLIWMachineScheduler.h:100
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::bumpCycle
void bumpCycle()
Move the boundary of scheduled code by one cycle.
Definition: VLIWMachineScheduler.cpp:387
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::releaseNode
void releaseNode(SUnit *SU, unsigned ReadyCycle)
Definition: VLIWMachineScheduler.cpp:372
llvm::ScheduleDAGInstrs::BB
MachineBasicBlock * BB
The block in which to insert instructions.
Definition: ScheduleDAGInstrs.h:146
llvm::ConvergingVLIWScheduler::createVLIWResourceModel
virtual VLIWResourceModel * createVLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const
Definition: VLIWMachineScheduler.cpp:305
llvm::ConvergingVLIWScheduler::SchedCandidate::RPDelta
RegPressureDelta RPDelta
Definition: VLIWMachineScheduler.h:97
llvm::ConvergingVLIWScheduler::SchedModel
const TargetSchedModel * SchedModel
Definition: VLIWMachineScheduler.h:208
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::isLatencyBound
bool isLatencyBound(SUnit *SU)
Definition: VLIWMachineScheduler.h:199
MachineScheduler.h
llvm::ConvergingVLIWScheduler::releaseTopNode
void releaseTopNode(SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling.
Definition: VLIWMachineScheduler.cpp:310
SmallVector.h
llvm::ConvergingVLIWScheduler::pickNodeFromQueue
CandResult pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)
Pick the best candidate from the top queue.
Definition: VLIWMachineScheduler.cpp:769
llvm::VLIWResourceModel::getPacketInstCount
size_t getPacketInstCount() const
Definition: VLIWMachineScheduler.h:60
llvm::ConvergingVLIWScheduler::MultiPressure
@ MultiPressure
Definition: VLIWMachineScheduler.h:111
llvm::VLIWMachineScheduler::VLIWMachineScheduler
VLIWMachineScheduler(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
Definition: VLIWMachineScheduler.h:71
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::pickOnlyChoice
SUnit * pickOnlyChoice()
If this queue only has one ready candidate, return it.
Definition: VLIWMachineScheduler.cpp:484
llvm::ConvergingVLIWScheduler::SchedCandidate::SU
SUnit * SU
Definition: VLIWMachineScheduler.h:94
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::removeReady
void removeReady(SUnit *SU)
Remove SU from the ready set for this boundary.
Definition: VLIWMachineScheduler.cpp:472
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:392
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::CheckPending
bool CheckPending
Definition: VLIWMachineScheduler.h:132
llvm::ReadyQueue
Helpers for implementing custom MachineSchedStrategy classes.
Definition: MachineScheduler.h:534
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::VLIWResourceModel::createPacketizer
virtual DFAPacketizer * createPacketizer(const TargetSubtargetInfo &STI) const
Definition: VLIWMachineScheduler.cpp:194
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::init
void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel)
Definition: VLIWMachineScheduler.h:155
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::~VLIWSchedBoundary
~VLIWSchedBoundary()
Definition: VLIWMachineScheduler.cpp:343
llvm::ConvergingVLIWScheduler::PriorityThree
static constexpr unsigned PriorityThree
Definition: VLIWMachineScheduler.h:120
llvm::ConvergingVLIWScheduler::~ConvergingVLIWScheduler
virtual ~ConvergingVLIWScheduler()=default
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::MinReadyCycle
unsigned MinReadyCycle
MinReadyCycle - Cycle of the soonest available instruction.
Definition: VLIWMachineScheduler.h:142