LLVM 23.0.0git
WebAssemblyRegisterBankInfo.h
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1//===- WebAssemblyRegisterBankInfo.h ----------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the RegisterBankInfo class for
10/// WebAssembly.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYREGISTERBANKINFO_H
15#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYREGISTERBANKINFO_H
16
18
19#define GET_REGBANK_DECLARATIONS
20#include "WebAssemblyGenRegisterBank.inc"
21
22namespace llvm {
23
24class TargetRegisterInfo;
25
27#define GET_TARGET_REGBANK_CLASS
28#include "WebAssemblyGenRegisterBank.inc"
29};
30
31/// This class provides the information for the target register banks.
40} // end namespace llvm
41#endif
IRTranslator LLVM IR MI
Register const TargetRegisterInfo * TRI
Representation of each machine instruction.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
WebAssemblyRegisterBankInfo(const TargetRegisterInfo &TRI)
This is an optimization pass for GlobalISel generic memory operations.
Definition Types.h:26