LLVM  9.0.0svn
BPFMCCodeEmitter.cpp
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1 //===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the BPFMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/MC/MCCodeEmitter.h"
16 #include "llvm/MC/MCFixup.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/Support/Endian.h"
23 #include <cassert>
24 #include <cstdint>
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "mccodeemitter"
29 
30 namespace {
31 
32 class BPFMCCodeEmitter : public MCCodeEmitter {
33  const MCInstrInfo &MCII;
34  const MCRegisterInfo &MRI;
35  bool IsLittleEndian;
36 
37 public:
38  BPFMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
39  bool IsLittleEndian)
40  : MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {}
41  BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete;
42  void operator=(const BPFMCCodeEmitter &) = delete;
43  ~BPFMCCodeEmitter() override = default;
44 
45  // getBinaryCodeForInstr - TableGen'erated function for getting the
46  // binary encoding for an instruction.
47  uint64_t getBinaryCodeForInstr(const MCInst &MI,
49  const MCSubtargetInfo &STI) const;
50 
51  // getMachineOpValue - Return binary encoding of operand. If the machin
52  // operand requires relocation, record the relocation and return zero.
53  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
55  const MCSubtargetInfo &STI) const;
56 
57  uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
59  const MCSubtargetInfo &STI) const;
60 
61  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
63  const MCSubtargetInfo &STI) const override;
64 
65 private:
66  uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
67  void verifyInstructionPredicates(const MCInst &MI,
68  uint64_t AvailableFeatures) const;
69 };
70 
71 } // end anonymous namespace
72 
74  const MCRegisterInfo &MRI,
75  MCContext &Ctx) {
76  return new BPFMCCodeEmitter(MCII, MRI, true);
77 }
78 
80  const MCRegisterInfo &MRI,
81  MCContext &Ctx) {
82  return new BPFMCCodeEmitter(MCII, MRI, false);
83 }
84 
85 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
86  const MCOperand &MO,
88  const MCSubtargetInfo &STI) const {
89  if (MO.isReg())
90  return MRI.getEncodingValue(MO.getReg());
91  if (MO.isImm())
92  return static_cast<unsigned>(MO.getImm());
93 
94  assert(MO.isExpr());
95 
96  const MCExpr *Expr = MO.getExpr();
97 
98  assert(Expr->getKind() == MCExpr::SymbolRef);
99 
100  if (MI.getOpcode() == BPF::JAL)
101  // func call name
102  Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_4));
103  else if (MI.getOpcode() == BPF::LD_imm64)
104  Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8));
105  else
106  // bb label
107  Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2));
108 
109  return 0;
110 }
111 
112 static uint8_t SwapBits(uint8_t Val)
113 {
114  return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
115 }
116 
117 void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
118  SmallVectorImpl<MCFixup> &Fixups,
119  const MCSubtargetInfo &STI) const {
120  verifyInstructionPredicates(MI,
121  computeAvailableFeatures(STI.getFeatureBits()));
122 
123  unsigned Opcode = MI.getOpcode();
125  IsLittleEndian ? support::little : support::big);
126 
127  if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
128  uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
129  OS << char(Value >> 56);
130  if (IsLittleEndian)
131  OS << char((Value >> 48) & 0xff);
132  else
133  OS << char(SwapBits((Value >> 48) & 0xff));
134  OSE.write<uint16_t>(0);
135  OSE.write<uint32_t>(Value & 0xffffFFFF);
136 
137  const MCOperand &MO = MI.getOperand(1);
138  uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
139  OSE.write<uint8_t>(0);
140  OSE.write<uint8_t>(0);
141  OSE.write<uint16_t>(0);
142  OSE.write<uint32_t>(Imm >> 32);
143  } else {
144  // Get instruction encoding and emit it
145  uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
146  OS << char(Value >> 56);
147  if (IsLittleEndian)
148  OS << char((Value >> 48) & 0xff);
149  else
150  OS << char(SwapBits((Value >> 48) & 0xff));
151  OSE.write<uint16_t>((Value >> 32) & 0xffff);
152  OSE.write<uint32_t>(Value & 0xffffFFFF);
153  }
154 }
155 
156 // Encode BPF Memory Operand
157 uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
158  SmallVectorImpl<MCFixup> &Fixups,
159  const MCSubtargetInfo &STI) const {
160  uint64_t Encoding;
161  const MCOperand Op1 = MI.getOperand(1);
162  assert(Op1.isReg() && "First operand is not register.");
163  Encoding = MRI.getEncodingValue(Op1.getReg());
164  Encoding <<= 16;
165  MCOperand Op2 = MI.getOperand(2);
166  assert(Op2.isImm() && "Second operand is not immediate.");
167  Encoding |= Op2.getImm() & 0xffff;
168  return Encoding;
169 }
170 
171 #define ENABLE_INSTR_PREDICATE_VERIFIER
172 #include "BPFGenMCCodeEmitter.inc"
bool isImm() const
Definition: MCInst.h:58
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isReg() const
Definition: MCInst.h:57
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:62
MCCodeEmitter * createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCExpr * getExpr() const
Definition: MCInst.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
int64_t getImm() const
Definition: MCInst.h:75
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
bool isExpr() const
Definition: MCInst.h:60
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:89
static uint8_t SwapBits(uint8_t Val)
A two-byte pc relative fixup.
Definition: MCFixup.h:28
A four-byte pc relative fixup.
Definition: MCFixup.h:29
void write(ArrayRef< value_type > Val)
Definition: EndianStream.h:55
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:51
A eight-byte section relative fixup.
Definition: MCFixup.h:42
Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:40
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
MCCodeEmitter * createBPFMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
unsigned getOpcode() const
Definition: MCInst.h:171
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34