LLVM  7.0.0svn
BPFMCCodeEmitter.cpp
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1 //===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the BPFMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/MC/MCCodeEmitter.h"
17 #include "llvm/MC/MCFixup.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
24 #include <cassert>
25 #include <cstdint>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "mccodeemitter"
30 
31 namespace {
32 
33 class BPFMCCodeEmitter : public MCCodeEmitter {
34  const MCInstrInfo &MCII;
35  const MCRegisterInfo &MRI;
36  bool IsLittleEndian;
37 
38 public:
39  BPFMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
40  bool IsLittleEndian)
41  : MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {}
42  BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete;
43  void operator=(const BPFMCCodeEmitter &) = delete;
44  ~BPFMCCodeEmitter() override = default;
45 
46  // getBinaryCodeForInstr - TableGen'erated function for getting the
47  // binary encoding for an instruction.
48  uint64_t getBinaryCodeForInstr(const MCInst &MI,
50  const MCSubtargetInfo &STI) const;
51 
52  // getMachineOpValue - Return binary encoding of operand. If the machin
53  // operand requires relocation, record the relocation and return zero.
54  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
56  const MCSubtargetInfo &STI) const;
57 
58  uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
60  const MCSubtargetInfo &STI) const;
61 
62  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
64  const MCSubtargetInfo &STI) const override;
65 
66 private:
67  uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
68  void verifyInstructionPredicates(const MCInst &MI,
69  uint64_t AvailableFeatures) const;
70 };
71 
72 } // end anonymous namespace
73 
75  const MCRegisterInfo &MRI,
76  MCContext &Ctx) {
77  return new BPFMCCodeEmitter(MCII, MRI, true);
78 }
79 
81  const MCRegisterInfo &MRI,
82  MCContext &Ctx) {
83  return new BPFMCCodeEmitter(MCII, MRI, false);
84 }
85 
86 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
87  const MCOperand &MO,
89  const MCSubtargetInfo &STI) const {
90  if (MO.isReg())
91  return MRI.getEncodingValue(MO.getReg());
92  if (MO.isImm())
93  return static_cast<unsigned>(MO.getImm());
94 
95  assert(MO.isExpr());
96 
97  const MCExpr *Expr = MO.getExpr();
98 
99  assert(Expr->getKind() == MCExpr::SymbolRef);
100 
101  if (MI.getOpcode() == BPF::JAL)
102  // func call name
103  Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_4));
104  else if (MI.getOpcode() == BPF::LD_imm64)
105  Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8));
106  else
107  // bb label
108  Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2));
109 
110  return 0;
111 }
112 
113 static uint8_t SwapBits(uint8_t Val)
114 {
115  return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
116 }
117 
118 void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
119  SmallVectorImpl<MCFixup> &Fixups,
120  const MCSubtargetInfo &STI) const {
121  verifyInstructionPredicates(MI,
122  computeAvailableFeatures(STI.getFeatureBits()));
123 
124  unsigned Opcode = MI.getOpcode();
126  IsLittleEndian ? support::little : support::big);
127 
128  if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
129  uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
130  OS << char(Value >> 56);
131  if (IsLittleEndian)
132  OS << char((Value >> 48) & 0xff);
133  else
134  OS << char(SwapBits((Value >> 48) & 0xff));
135  OSE.write<uint16_t>(0);
136  OSE.write<uint32_t>(Value & 0xffffFFFF);
137 
138  const MCOperand &MO = MI.getOperand(1);
139  uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
140  OSE.write<uint8_t>(0);
141  OSE.write<uint8_t>(0);
142  OSE.write<uint16_t>(0);
143  OSE.write<uint32_t>(Imm >> 32);
144  } else {
145  // Get instruction encoding and emit it
146  uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
147  OS << char(Value >> 56);
148  if (IsLittleEndian)
149  OS << char((Value >> 48) & 0xff);
150  else
151  OS << char(SwapBits((Value >> 48) & 0xff));
152  OSE.write<uint16_t>((Value >> 32) & 0xffff);
153  OSE.write<uint32_t>(Value & 0xffffFFFF);
154  }
155 }
156 
157 // Encode BPF Memory Operand
158 uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
159  SmallVectorImpl<MCFixup> &Fixups,
160  const MCSubtargetInfo &STI) const {
161  uint64_t Encoding;
162  const MCOperand Op1 = MI.getOperand(1);
163  assert(Op1.isReg() && "First operand is not register.");
164  Encoding = MRI.getEncodingValue(Op1.getReg());
165  Encoding <<= 16;
166  MCOperand Op2 = MI.getOperand(2);
167  assert(Op2.isImm() && "Second operand is not immediate.");
168  Encoding |= Op2.getImm() & 0xffff;
169  return Encoding;
170 }
171 
172 #define ENABLE_INSTR_PREDICATE_VERIFIER
173 #include "BPFGenMCCodeEmitter.inc"
bool isImm() const
Definition: MCInst.h:59
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isReg() const
Definition: MCInst.h:58
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
MCCodeEmitter * createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCExpr * getExpr() const
Definition: MCInst.h:96
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
int64_t getImm() const
Definition: MCInst.h:76
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
bool isExpr() const
Definition: MCInst.h:61
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:90
static uint8_t SwapBits(uint8_t Val)
A two-byte pc relative fixup.
Definition: MCFixup.h:29
A four-byte pc relative fixup.
Definition: MCFixup.h:30
void write(ArrayRef< value_type > Val)
Definition: EndianStream.h:56
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:52
A eight-byte section relative fixup.
Definition: MCFixup.h:43
Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:41
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
MCCodeEmitter * createBPFMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
unsigned getOpcode() const
Definition: MCInst.h:174
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35